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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PP0101] rtl/fifo4.v:57 Cannot open include file "timescale.v".

[ERROR:PP0101] rtl/simple_spi_top.v:74 Cannot open include file "timescale.v".

[WARNI:PA0205] cache/synth.v:1 No timescale set for "\\\$paramod\fifo4\dw=8\\\".

[WARNI:PA0205] cache/synth.v:282 No timescale set for "simple_spi_top".

[WARNI:PA0205] timescale.v:5 No timescale set for "fifo4".

[INFO :CP0300] Compilation...

[INFO :CP0303] timescale.v:5 Compile module "work@fifo4".

[INFO :CP0303] cache/synth.v:1 Compile module "work@\\\$paramod\fifo4\dw=8\\\".

[INFO :CP0303] cache/synth.v:282 Compile module "work@simple_spi_top".

[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout",
there are 2 more instances of this message.

[NOTE :CP0309] timescale.v:5 Implicit port type (wire) for "dout",
there are 2 more instances of this message.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] cache/synth.v:1 Top level module "work@\\\$paramod\fifo4\dw=8\\\".

[NOTE :EL0503] cache/synth.v:282 Top level module "work@simple_spi_top".

[NOTE :EL0504] Multiple top level modules in design.

[WARNI:EL0500] cache/synth.v:1191 Cannot find a module definition for "work@simple_spi_top::\\\$paramod\fifo4\dw=8 \\\".

[WARNI:EL0500] cache/synth.v:1202 Cannot find a module definition for "work@simple_spi_top::\\\$paramod\fifo4\dw=8 \\\".

[NOTE :EL0508] Nb Top level modules: 2.

[NOTE :EL0509] Max instance depth: 2.

[NOTE :EL0510] Nb instances: 4.

[NOTE :EL0511] Nb leaf instances: 3.

[WARNI:EL0512] Nb undefined modules: 1.

[WARNI:EL0513] Nb undefined instances: 2.

[  FATAL] : 0
[  ERROR] : 2
[WARNING] : 7
[   NOTE] : 9

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*   End SURELOG SVerilog Compiler/Linter   *
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3.46user 0.07system 0:01.33elapsed 264%CPU (0avgtext+0avgdata 72876maxresident)k
0inputs+184outputs (0major+15499minor)pagefaults 0swaps