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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[ERROR:PP0101] rtl/pcm_slv_top.v:65 Cannot open include file "timescale.v".

[WARNI:PA0205] cache/synth.v:1 No timescale set for "pcm_slv_top".

[INFO :CP0300] Compilation...

[INFO :CP0303] cache/synth.v:1 Compile module "work@pcm_slv_top".

[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout_o".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] cache/synth.v:1 Top level module "work@pcm_slv_top".

[WARNI:EL0505] timescale.v:11 Multiply defined module "work@pcm_slv_top",
               cache/synth.v:1 previous definition.

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 1.

[NOTE :EL0510] Nb instances: 1.

[NOTE :EL0511] Nb leaf instances: 1.

[  FATAL] : 0
[  ERROR] : 1
[WARNING] : 2
[   NOTE] : 6

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*   End SURELOG SVerilog Compiler/Linter   *
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1.36user 0.01system 0:00.91elapsed 151%CPU (0avgtext+0avgdata 47912maxresident)k
0inputs+112outputs (0major+9354minor)pagefaults 0swaps