read_verilog ../common/adffs.v
design -save read

hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFR
select -assert-none t:SB_DFFR %% t:* %D

design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFR
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D

design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFSS
select -assert-none t:SB_DFFSS %% t:* %D

design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFNSR
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D