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foss-fpga-tools / third_party / Surelog / refs/heads/mithro-patch-1
commite911119afa19222dc9bbad9ba934f3d965e34302[log] [tgz]
authorTim Ansell <me@mith.ro>Mon Nov 04 15:00:38 2019 -0700
committerGitHub <noreply@github.com>Mon Nov 04 15:00:38 2019 -0700
tree0087e3bdcbc174f70c8dc12cc62ebaad7dabfa3c
parent356a4bf2123fc606ca19fbed9b9c535f149fdec5 [diff]
Small updates to README.

 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
1 file changed
tree: 0087e3bdcbc174f70c8dc12cc62ebaad7dabfa3c
  1. G4/
  2. SVIncCompil/
  3. third_party/
  4. UVM/
  5. .gitignore
  6. .travis.yml
  7. HEADER
  8. LICENSE
  9. Makefile
  10. NOTICE
  11. README.md
README.md

Surelog

System Verilog 2017 Pre-processor, Parser

Goal

This project aims at providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.

Applications

Linter, Simulator, Synthesys tool, Formal tools can use this front-end and be developed either as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk memory models (down-converter).

Contributing to this project

This project is open to contributions from any user! From the commercial vendor to the Verilog enthousiast are welcome.

Features

  • The preprocessor and the parser use Antlr 4.72 as a parser generator.
  • The preprocessor and the parser ASTs are made persistent on disk using Google Flatbuffers, enabling incremental compilation.
  • The tool is built thread safe and performs multithread parsing.
  • Large files/modules/packages are splitted for multi-threading compilation.
  • Surelog accepts IEEE Simulator-compliant project specification.
  • Surelog issues Errors/Warning/Info/Notes about language compliance.
  • Surelog allows for pre-compiled packages (UVM,...).

Build instructions and test:

make

For more build/test options and system requirements for building see SVIncCompil/README file.