Surelog license will expire 9/30/2019
********************************************
*  SURELOG System Verilog Compiler/Linter  *
********************************************

[INFO :CM0023] Creating log file sim/simv/slpp_unit/surelog.log.

[WARNI:CM0010] Command line argument "-full64" ignored.

[WARNI:CM0010] Command line argument "-PP" ignored.

[WARNI:CM0010] Command line argument "-notice" ignored.

[WARNI:CM0010] Command line argument "-line" ignored.

[NOTE :CM0009] Command line argument "+lint=all,noVCDE,noUI" ignored.

[NOTE :CM0009] Command line argument "+v2k" ignored.

[WARNI:CM0010] Command line argument "-quiet" ignored.

[WARNI:CM0010] Command line argument "-debug_pp" ignored.

[WARNI:CM0010] Command line argument "-Mdirectory=sim/csrc" ignored.

[NOTE :CM0009] Command line argument "+vc+list" ignored.

[WARNI:CM0010] Command line argument "-CC" ignored.

[WARNI:CM0010] Command line argument "-I/include" ignored.

[WARNI:CM0010] Command line argument "-std=c++11" ignored.

[INFO :CM0020] Separate compilation-unit mode is on.

[INFO :CM0024] Executing with 4 threads.

Scan libraries took 0.000000s

[NOTE :PP0105] src/main/verilog/vscale_ctrl_constants.vh, line 42: Multiply defined macro "MEM_TYPE_WIDTH",
               src/main/verilog/vscale_ctrl_constants.vh, line 33: previous definition.

Preprocessing took 0.072000s

Parsing took 1.122000s
For file sim/simv/slpp_unit/work/__/__/__/dist/Release/GNU-Linux/__/sv/builtin.sv, Tokenizer took 0.006000
For file sim/simv/slpp_unit/work/__/__/__/dist/Release/GNU-Linux/__/sv/builtin.sv, SSL Parsing took 0.044000
For file sim/simv/slpp_unit/work/__/__/__/dist/Release/GNU-Linux/__/sv/builtin.sv, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_hex_tb.v, Tokenizer took 0.008000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_hex_tb.v, SSL Parsing took 1.004000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_hex_tb.v, AST Walking took 0.002000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_sim_top.v, Tokenizer took 0.010000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_sim_top.v, SSL Parsing took 0.276000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_sim_top.v, AST Walking took 0.002000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_dp_hasti_sram.v, Tokenizer took 0.010000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_dp_hasti_sram.v, SSL Parsing took 0.628000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_dp_hasti_sram.v, AST Walking took 0.004000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_core.v, Tokenizer took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_core.v, SSL Parsing took 0.228000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_core.v, AST Walking took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_hasti_bridge.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_hasti_bridge.v, SSL Parsing took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_hasti_bridge.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_pipeline.v, Tokenizer took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_pipeline.v, SSL Parsing took 0.082000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_pipeline.v, AST Walking took 0.004000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_ctrl.v, Tokenizer took 0.006000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_ctrl.v, SSL Parsing took 0.290000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_ctrl.v, AST Walking took 0.010000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_regfile.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_regfile.v, SSL Parsing took 0.250000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_regfile.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_a_mux.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_a_mux.v, SSL Parsing took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_a_mux.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_b_mux.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_b_mux.v, SSL Parsing took 0.020000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_b_mux.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_imm_gen.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_imm_gen.v, SSL Parsing took 0.020000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_imm_gen.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_alu.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_alu.v, SSL Parsing took 0.306000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_alu.v, AST Walking took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_mul_div.v, Tokenizer took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_mul_div.v, SSL Parsing took 0.216000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_mul_div.v, AST Walking took 0.004000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_csr_file.v, Tokenizer took 0.006000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_csr_file.v, SSL Parsing took 0.472000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_csr_file.v, AST Walking took 0.008000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_PC_mux.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_PC_mux.v, SSL Parsing took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_PC_mux.v, AST Walking took 0.002000

[WARNI:PA0205] src/main/verilog/vscale_core.v, line 5: No timescale set for "vscale_core".

[WARNI:PA0205] src/test/verilog/vscale_sim_top.v, line 4: No timescale set for "vscale_sim_top".

[WARNI:PA0205] src/main/verilog/vscale_src_b_mux.v, line 5: No timescale set for "vscale_src_b_mux".

[WARNI:PA0205] src/main/verilog/vscale_regfile.v, line 2: No timescale set for "vscale_regfile".

[WARNI:PA0205] src/main/verilog/vscale_src_a_mux.v, line 5: No timescale set for "vscale_src_a_mux".

[WARNI:PA0205] src/main/verilog/vscale_imm_gen.v, line 5: No timescale set for "vscale_imm_gen".

[WARNI:PA0205] src/main/verilog/vscale_alu.v, line 5: No timescale set for "vscale_alu".

[WARNI:PA0205] src/test/verilog/vscale_dp_hasti_sram.v, line 2: No timescale set for "vscale_dp_hasti_sram".

[WARNI:PA0205] src/main/verilog/vscale_mul_div.v, line 4: No timescale set for "vscale_mul_div".

[WARNI:PA0205] src/main/verilog/vscale_PC_mux.v, line 5: No timescale set for "vscale_PC_mux".

[WARNI:PA0205] src/main/verilog/vscale_ctrl.v, line 6: No timescale set for "vscale_ctrl".

[WARNI:PA0205] src/test/verilog/vscale_hex_tb.v, line 3: No timescale set for "vscale_hex_tb".

[WARNI:PA0205] src/main/verilog/vscale_hasti_bridge.v, line 4: No timescale set for "vscale_hasti_bridge".

[WARNI:PA0205] src/main/verilog/vscale_csr_file.v, line 5: No timescale set for "vscale_csr_file".

[WARNI:PA0205] src/main/verilog/vscale_pipeline.v, line 7: No timescale set for "vscale_pipeline".

[INFO :CP0300] Compilation...

[INFO :CP0303] src/main/verilog/vscale_PC_mux.v, line 5: Compile module "work@vscale_PC_mux".

[INFO :CP0303] src/main/verilog/vscale_alu.v, line 5: Compile module "work@vscale_alu".

[INFO :CP0303] src/main/verilog/vscale_core.v, line 5: Compile module "work@vscale_core".

[INFO :CP0303] src/main/verilog/vscale_csr_file.v, line 5: Compile module "work@vscale_csr_file".

[INFO :CP0303] src/main/verilog/vscale_ctrl.v, line 6: Compile module "work@vscale_ctrl".

[INFO :CP0303] src/test/verilog/vscale_dp_hasti_sram.v, line 2: Compile module "work@vscale_dp_hasti_sram".

[INFO :CP0303] src/main/verilog/vscale_hasti_bridge.v, line 4: Compile module "work@vscale_hasti_bridge".

[INFO :CP0303] src/test/verilog/vscale_hex_tb.v, line 3: Compile module "work@vscale_hex_tb".

[INFO :CP0303] src/main/verilog/vscale_imm_gen.v, line 5: Compile module "work@vscale_imm_gen".

[INFO :CP0303] src/main/verilog/vscale_mul_div.v, line 4: Compile module "work@vscale_mul_div".

[INFO :CP0303] src/main/verilog/vscale_pipeline.v, line 7: Compile module "work@vscale_pipeline".

[INFO :CP0303] src/main/verilog/vscale_regfile.v, line 2: Compile module "work@vscale_regfile".

[INFO :CP0303] src/test/verilog/vscale_sim_top.v, line 4: Compile module "work@vscale_sim_top".

[INFO :CP0303] src/main/verilog/vscale_src_a_mux.v, line 5: Compile module "work@vscale_src_a_mux".

[INFO :CP0303] src/main/verilog/vscale_src_b_mux.v, line 5: Compile module "work@vscale_src_b_mux".

[INFO :CP0302] ../../../dist/Release/GNU-Linux/../sv/builtin.sv, line 4: Compile class "work@mailbox".

[INFO :CP0302] ../../../dist/Release/GNU-Linux/../sv/builtin.sv, line 33: Compile class "work@process".

[INFO :CP0302] ../../../dist/Release/GNU-Linux/../sv/builtin.sv, line 58: Compile class "work@semaphore".

[NOTE :CP0309] src/main/verilog/vscale_core.v, line 8: Implicit port type (wire) for "clk",
               there are 20 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_csr_file.v, line 8: Implicit port type (wire) for "clk",
               there are 12 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_ctrl.v, line 7: Implicit port type (wire) for "clk",
               there are 14 more instances of this message.

[NOTE :CP0309] src/test/verilog/vscale_dp_hasti_sram.v, line 3: Implicit port type (wire) for "hclk",
               there are 9 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_hasti_bridge.v, line 6: Implicit port type (wire) for "hwrite",
               there are 6 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_mul_div.v, line 5: Implicit port type (wire) for "clk",
               there are 6 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_pipeline.v, line 10: Implicit port type (wire) for "clk",
               there are 13 more instances of this message.

[NOTE :CP0309] src/main/verilog/vscale_regfile.v, line 5: Implicit port type (wire) for "clk",
               there are 1 more instances of this message.

[NOTE :CP0309] src/test/verilog/vscale_sim_top.v, line 5: Implicit port type (wire) for "clk",
               there are 6 more instances of this message.

Compilation took 0.004000s

[INFO :EL0526] Design Elaboration...

Instance tree:
[TOP] work@vscale_hex_tb work@vscale_hex_tb
[MOD] work@vscale_sim_top work@vscale_hex_tb.DUT
[SCO] work@vscale_hex_tb.UNNAMED work@vscale_hex_tb.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED work@vscale_hex_tb.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED work@vscale_hex_tb.UNNAMED
[MOD] work@vscale_core work@vscale_hex_tb.DUT.vscale
[MOD] work@vscale_dp_hasti_sram work@vscale_hex_tb.DUT.hasti_mem
[SCO] work@vscale_hex_tb.UNNAMED.UNNAMED work@vscale_hex_tb.UNNAMED.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED.UNNAMED work@vscale_hex_tb.UNNAMED.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED.UNNAMED work@vscale_hex_tb.UNNAMED.UNNAMED
[MOD] work@vscale_hasti_bridge work@vscale_hex_tb.DUT.vscale.imem_bridge
[MOD] work@vscale_hasti_bridge work@vscale_hex_tb.DUT.vscale.dmem_bridge
[MOD] work@vscale_pipeline work@vscale_hex_tb.DUT.vscale.pipeline
[SCO] work@vscale_dp_hasti_sram.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED
[SCO] work@vscale_dp_hasti_sram.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED
[MOD] work@vscale_ctrl work@vscale_hex_tb.DUT.vscale.pipeline.ctrl
[MOD] work@vscale_PC_mux work@vscale_hex_tb.DUT.vscale.pipeline.PCmux
[SCO] work@vscale_pipeline.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED
[MOD] work@vscale_regfile work@vscale_hex_tb.DUT.vscale.pipeline.regfile
[MOD] work@vscale_imm_gen work@vscale_hex_tb.DUT.vscale.pipeline.imm_gen
[MOD] work@vscale_src_a_mux work@vscale_hex_tb.DUT.vscale.pipeline.src_a_mux
[MOD] work@vscale_src_b_mux work@vscale_hex_tb.DUT.vscale.pipeline.src_b_mux
[MOD] work@vscale_alu work@vscale_hex_tb.DUT.vscale.pipeline.alu
[MOD] work@vscale_mul_div work@vscale_hex_tb.DUT.vscale.pipeline.md
[SCO] work@vscale_pipeline.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED
[MOD] work@vscale_csr_file work@vscale_hex_tb.DUT.vscale.pipeline.csr
[SCO] work@vscale_dp_hasti_sram.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED
[SCO] work@vscale_dp_hasti_sram.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED
[SCO] work@vscale_dp_hasti_sram.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED
[SCO] work@vscale_dp_hasti_sram.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED
[SCO] work@vscale_PC_mux.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED
[SCO] work@vscale_regfile.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.regfile.UNNAMED
[SCO] work@vscale_regfile.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.regfile.UNNAMED
[SCO] work@vscale_imm_gen.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.imm_gen.UNNAMED
[SCO] work@vscale_src_a_mux.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.src_a_mux.UNNAMED
[SCO] work@vscale_src_b_mux.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.src_b_mux.UNNAMED
[SCO] work@vscale_alu.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.alu.UNNAMED
[SCO] work@vscale_mul_div.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED
[SCO] work@vscale_mul_div.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED
[SCO] work@vscale_mul_div.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED
[SCO] work@vscale_mul_div.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED
[SCO] work@vscale_pipeline.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_csr_file.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED
[SCO] work@vscale_dp_hasti_sram.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_dp_hasti_sram.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_dp_hasti_sram.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
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[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
[SCO] work@vscale_ctrl.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED
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[SCO] work@vscale_PC_mux.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED.UNNAMED
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[SCO] work@vscale_pipeline.UNNAMED.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED.UNNAMED
[SCO] work@vscale_regfile.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.regfile.UNNAMED.UNNAMED
[SCO] work@vscale_regfile.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.regfile.UNNAMED.UNNAMED
[SCO] work@vscale_mul_div.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED
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[SCO] work@vscale_csr_file.UNNAMED.UNNAMED work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED
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[NOTE :EL0503] src/test/verilog/vscale_hex_tb.v, line 3: Top level module "work@vscale_hex_tb".

[NOTE :EL0508] Nb Top level modules: 1.

[NOTE :EL0509] Max instance depth: 5.

[NOTE :EL0510] Nb instances: 16.

[NOTE :EL0511] Nb leaf instances: 2.

[NOTE :EL0523] src/test/verilog/vscale_hex_tb.v, line 3: Instance "work@vscale_hex_tb".

[NOTE :EL0523] src/test/verilog/vscale_hex_tb.v, line 24: Instance "work@vscale_hex_tb.DUT".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 37: Scope "work@vscale_hex_tb.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 47: Scope "work@vscale_hex_tb.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 65: Scope "work@vscale_hex_tb.UNNAMED".

[NOTE :EL0523] src/test/verilog/vscale_sim_top.v, line 58: Instance "work@vscale_hex_tb.DUT.vscale".

[NOTE :EL0523] src/test/verilog/vscale_sim_top.v, line 102: Instance "work@vscale_hex_tb.DUT.hasti_mem".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 51: Scope "work@vscale_hex_tb.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 71: Scope "work@vscale_hex_tb.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 84: Scope "work@vscale_hex_tb.UNNAMED.UNNAMED".

[NOTE :EL0523] src/main/verilog/vscale_core.v, line 69: Instance "work@vscale_hex_tb.DUT.vscale.imem_bridge".

[NOTE :EL0523] src/main/verilog/vscale_core.v, line 91: Instance "work@vscale_hex_tb.DUT.vscale.dmem_bridge".

[NOTE :EL0523] src/main/verilog/vscale_core.v, line 114: Instance "work@vscale_hex_tb.DUT.vscale.pipeline".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 57: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 102: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 53: Scope "work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 72: Scope "work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 40: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 56: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 145: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 194: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 207: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 215: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 232: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.regfile".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 243: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.imm_gen".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 249: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.src_a_mux".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 256: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.src_b_mux".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 266: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.alu".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 273: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.md".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 294: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 309: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 321: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED".

[NOTE :EL0523] src/main/verilog/vscale_pipeline.v, line 340: Instance "work@vscale_hex_tb.DUT.vscale.pipeline.csr".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 59: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 66: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 104: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 106: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 54: Scope "work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 73: Scope "work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_hex_tb.v, line 76: Scope "work@vscale_hex_tb.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 133: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 149: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 173: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 203: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 349: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 390: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 416: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 436: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 470: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_PC_mux.v, line 23: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 208: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 210: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 216: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 219: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_regfile.v, line 24: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.regfile.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_regfile.v, line 31: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.regfile.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_imm_gen.v, line 11: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.imm_gen.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_src_a_mux.v, line 13: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.src_a_mux.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_src_b_mux.v, line 13: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.src_b_mux.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_alu.v, line 16: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.alu.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 50: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 69: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 77: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 87: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 295: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 299: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 108: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 125: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 134: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 143: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 169: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 191: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 209: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 217: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 226: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 248: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 255: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 263: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 300: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 67: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 71: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 107: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 134: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 136: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 150: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 153: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 175: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 177: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 179: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 181: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 183: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 227: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 232: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 238: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 252: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 259: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 266: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 283: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 287: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 297: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 326: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 332: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 338: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 355: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 357: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 362: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 366: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 369: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 374: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 377: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 383: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 417: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 419: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 421: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 423: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 425: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 427: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 429: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 437: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 445: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 472: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_PC_mux.v, line 25: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_PC_mux.v, line 29: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_PC_mux.v, line 33: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_PC_mux.v, line 37: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_PC_mux.v, line 41: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_PC_mux.v, line 45: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_PC_mux.v, line 49: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.PCmux.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 220: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_pipeline.v, line 222: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_regfile.v, line 25: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.regfile.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_regfile.v, line 32: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.regfile.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 70: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 72: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 89: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 100: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 115: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 110: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 112: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 147: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 153: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 170: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 172: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 174: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 177: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 192: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 195: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 210: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 212: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 227: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 230: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 233: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 265: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 266: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 267: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 268: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 269: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 270: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 271: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 272: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 273: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 274: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 275: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 276: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 277: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 278: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 279: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 280: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 281: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 282: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 283: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 284: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 285: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 286: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 287: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 288: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 289: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 290: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 291: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 293: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 294: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 295: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 301: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 311: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 72: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 80: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 108: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 109: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 268: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 274: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 292: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 301: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 473: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 90: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 103: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 107: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 148: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 154: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 200: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 234: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 237: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 317: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_csr_file.v, line 351: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.csr.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/test/verilog/vscale_dp_hasti_sram.v, line 76: Scope "work@vscale_hex_tb.DUT.hasti_mem.UNNAMED.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 302: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 104: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_mul_div.v, line 109: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.md.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

[NOTE :EL0522] src/main/verilog/vscale_ctrl.v, line 306: Scope "work@vscale_hex_tb.DUT.vscale.pipeline.ctrl.UNNAMED.UNNAMED.UNNAMED.UNNAMED.UNNAMED".

Elaboration took 0.006000s

==============
PROFILE
==============
Scan libraries took 0.000000s
Preprocessing took 0.072000s
Parsing took 1.122000s
For file sim/simv/slpp_unit/work/__/__/__/dist/Release/GNU-Linux/__/sv/builtin.sv, Tokenizer took 0.006000
For file sim/simv/slpp_unit/work/__/__/__/dist/Release/GNU-Linux/__/sv/builtin.sv, SSL Parsing took 0.044000
For file sim/simv/slpp_unit/work/__/__/__/dist/Release/GNU-Linux/__/sv/builtin.sv, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_hex_tb.v, Tokenizer took 0.008000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_hex_tb.v, SSL Parsing took 1.004000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_hex_tb.v, AST Walking took 0.002000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_sim_top.v, Tokenizer took 0.010000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_sim_top.v, SSL Parsing took 0.276000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_sim_top.v, AST Walking took 0.002000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_dp_hasti_sram.v, Tokenizer took 0.010000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_dp_hasti_sram.v, SSL Parsing took 0.628000
For file sim/simv/slpp_unit/work/src/test/verilog/vscale_dp_hasti_sram.v, AST Walking took 0.004000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_core.v, Tokenizer took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_core.v, SSL Parsing took 0.228000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_core.v, AST Walking took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_hasti_bridge.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_hasti_bridge.v, SSL Parsing took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_hasti_bridge.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_pipeline.v, Tokenizer took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_pipeline.v, SSL Parsing took 0.082000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_pipeline.v, AST Walking took 0.004000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_ctrl.v, Tokenizer took 0.006000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_ctrl.v, SSL Parsing took 0.290000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_ctrl.v, AST Walking took 0.010000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_regfile.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_regfile.v, SSL Parsing took 0.250000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_regfile.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_a_mux.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_a_mux.v, SSL Parsing took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_a_mux.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_b_mux.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_b_mux.v, SSL Parsing took 0.020000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_src_b_mux.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_imm_gen.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_imm_gen.v, SSL Parsing took 0.020000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_imm_gen.v, AST Walking took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_alu.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_alu.v, SSL Parsing took 0.306000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_alu.v, AST Walking took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_mul_div.v, Tokenizer took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_mul_div.v, SSL Parsing took 0.216000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_mul_div.v, AST Walking took 0.004000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_csr_file.v, Tokenizer took 0.006000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_csr_file.v, SSL Parsing took 0.472000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_csr_file.v, AST Walking took 0.008000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_PC_mux.v, Tokenizer took 0.000000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_PC_mux.v, SSL Parsing took 0.002000
For file sim/simv/slpp_unit/work/src/main/verilog/vscale_PC_mux.v, AST Walking took 0.002000
Compilation took 0.004000s
Elaboration took 0.006000s
Total time 1.206000s
==============

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 25
[   NOTE] : 226

********************************************
*   End SURELOG SVerilog Compiler/Linter   *
********************************************