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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[INFO :PP0122] Preprocessing source file "/home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv".

[INFO :PP0122] Preprocessing source file "top.v".

[INFO :PP0122] Preprocessing source file "top1.v".

[INFO :PA0201] Parsing source file "/home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv".

[INFO :PA0201] Parsing source file "top.v".

[INFO :PA0201] Parsing source file "top1.v".

[WARNI:PA0205] top.v:13 No timescale set for "bottom2".

[WARNI:PA0205] top1.v:2 No timescale set for "my_interface".

[WARNI:PA0205] top1.v:32 No timescale set for "splice1".

[ERROR:PA0206] top.v:13 Missing timeunit/timeprecision for "bottom2".

[ERROR:PA0206] top.v:22 Missing timeunit/timeprecision for "bottom3".

[ERROR:PA0206] top.v:86 Missing timeunit/timeprecision for "bottom4".

[ERROR:PA0206] top1.v:2 Missing timeunit/timeprecision for "my_interface".

[ERROR:PA0206] top1.v:32 Missing timeunit/timeprecision for "splice1".

[INFO :CP0300] Compilation...

[INFO :CP0303] top.v:3 Compile module "work@bottom1".

[INFO :CP0303] top.v:13 Compile module "work@bottom2".

[INFO :CP0303] top.v:22 Compile module "work@bottom3".

[INFO :CP0303] top.v:86 Compile module "work@bottom4".

[INFO :CP0303] top1.v:283 Compile module "work@middle".

[INFO :CP0303] top1.v:287 Compile module "work@middle::nested".

[INFO :CP0304] top1.v:2 Compile interface "work@my_interface".

[INFO :CP0303] top1.v:32 Compile module "work@splice1".

[INFO :CP0303] top1.v:265 Compile module "work@top".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".

[ERROR:CP0334] top1.v:122 Colliding compilation unit name: "splice1",
               top1.v:32 previous usage.

[ERROR:CP0334] top1.v:194 Colliding compilation unit name: "splice1",
               top1.v:32 previous usage.

[ERROR:CP0334] top1.v:253 Colliding compilation unit name: "splice1",
               top1.v:32 previous usage.

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] top1.v:32 Top level module "work@splice1".

[NOTE :EL0503] top1.v:265 Top level module "work@top".

[WARNI:EL0505] top1.v:272 Multiply defined module "work@bottom1",
               top.v:3 previous definition.

[WARNI:EL0505] top1.v:277 Multiply defined module "work@bottom2",
               top.v:13 previous definition.

[WARNI:EL0505] top1.v:297 Multiply defined module "work@bottom3",
               top.v:22 previous definition.

[WARNI:EL0505] top1.v:122 Multiply defined module "work@splice1",
               top1.v:32 previous definition,
               top1.v:194 previous definition,
               top1.v:253 previous definition.

[NOTE :EL0504] Multiple top level modules in design.

[WARNI:EL0500] top.v:24 Cannot find a module definition for "work@bottom3::ddr".

[NOTE :EL0508] Nb Top level modules: 2.

[NOTE :EL0509] Max instance depth: 4.

[NOTE :EL0510] Nb instances: 8.

[NOTE :EL0511] Nb leaf instances: 4.

[WARNI:EL0512] Nb undefined modules: 1.

[WARNI:EL0513] Nb undefined instances: 1.

[  FATAL] : 0
[  ERROR] : 8
[WARNING] : 10
[   NOTE] : 7

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*   End SURELOG SVerilog Compiler/Linter   *
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0.61user 0.03system 0:00.66elapsed 97%CPU (0avgtext+0avgdata 50580maxresident)k
16inputs+120outputs (0major+14977minor)pagefaults 0swaps