# Verilog CAM: Content Addressable Memory

Source: https://github.com/alexforencich/verilog-cam

Two designs:

- **CAM_SRL_TOP** 64 bit data content by 32 entry content addressable memory
  built out of shift registers.

- **CAM_BRAM_TOP** 64 bit data content by 32 entry content addressable memory
  built out of block RAMs.