commit c59638c624d794e845cf00cd90ca6fc1ec5f37b5
author Clifford Wolf <clifford@clifford.at> Thu Aug 15 13:29:46 2019 +0200
committer GitHub <noreply@github.com> Thu Aug 15 13:29:46 2019 +0200
tree 7b7433f1ed5884ea998df31a55aebfed7b4061a8
parent 2ccae0d3864fd7268118287a85963c0116745cff
parent 26a40d0e114c5f9025718b511d45f2da09259c1c

Merge pull request #229 from tpambor/win-piping

Fix piping on windows

icebox/icebox_vlog.py

diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py
index 184cb03..a2c7950 100755
--- a/icebox/icebox_vlog.py
+++ b/icebox/icebox_vlog.py
@@ -750,8 +750,9 @@
         text_func.append("SB_RAM40_4K%s%s #(" % ("NR" if negclk_rd else "", "NW" if negclk_wr else ""));
         text_func.append("  .READ_MODE(%d)," % ((1 if get_ram_config('CBIT_2') else 0) + (2 if get_ram_config('CBIT_3') else 0)));
         text_func.append("  .WRITE_MODE(%d)," % ((1 if get_ram_config('CBIT_0') else 0) + (2 if get_ram_config('CBIT_1') else 0)));
-        for i in range(16):
-            text_func.append("  .INIT_%X(256'h%s)%s" % (i, ic.ram_data[tile][i], "," if i < 15 else ""));
+        if tile in ic.ram_data:
+            for i in range(16):
+                text_func.append("  .INIT_%X(256'h%s)%s" % (i, ic.ram_data[tile][i], "," if i < 15 else ""));
         text_func.append(") ram40_%d_%d (" % tile);
         text_func.append("  .WADDR(%s),"  % get_ram_wire('WADDR', 10, 0))
         text_func.append("  .RADDR(%s),"  % get_ram_wire('RADDR', 10, 0))

icepack/icepack.cc

diff --git a/icepack/icepack.cc b/icepack/icepack.cc
index 5b1745a..d441042 100644
--- a/icepack/icepack.cc
+++ b/icepack/icepack.cc
@@ -912,7 +912,7 @@
 			ofs << '\n';
 		}
 
-		if (cic.tile_type == "ramb")
+		if (cic.tile_type == "ramb" && !this->bram.empty())
 		{
 			BramIndexConverter bic(this, x, y);
 			ofs << stringf(".ram_data %d %d\n", x, y);