diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index cc7be01..195c08a 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -969,10 +969,15 @@
             last_dsp_y = 23
         else:
             assert False, "unknown DSP y " + str(y)
-        wire_signextin = add_wire(x, last_dsp_y, "dsp/signextout")
-        wire_signextout = add_wire(x, y, "dsp/signextout")
-        wire_accumci = add_wire(x, last_dsp_y, "dsp/accumco")
-        wire_accumco = add_wire(x, y, "dsp/accumco")
+        def add_if_new(x, y, name):
+            if (x, y, name) in wire_names:
+                return wire_names[(x, y, name)]
+            else:
+                return add_wire(x, y, name)
+        wire_signextin = add_if_new(x, last_dsp_y, "dsp/signextout")
+        wire_signextout = add_if_new(x, y, "dsp/signextout")
+        wire_accumci = add_if_new(x, last_dsp_y, "dsp/accumco")
+        wire_accumco = add_if_new(x, y, "dsp/accumco")
         add_bel_input(bel, wire_signextin, "SIGNEXTIN")
         add_bel_output(bel, wire_signextout, "SIGNEXTOUT")
         add_bel_input(bel, wire_accumci, "ACCUMCI")