diff --git a/verible/verilog/formatting/formatter_issue_regression_test.cc b/verible/verilog/formatting/formatter_issue_regression_test.cc
index 8f1fcef..b952cd9 100644
--- a/verible/verilog/formatting/formatter_issue_regression_test.cc
+++ b/verible/verilog/formatting/formatter_issue_regression_test.cc
@@ -314,6 +314,23 @@
     EXPECT_EQ(stream.str(), test_case.expected) << "code:\n" << test_case.input;
   }
 }
+
+// Regression for https://github.com/chipsalliance/verible/issues/2607:
+// A CRLF macro definition must keep a single line terminator so formatting
+// converges.
+TEST(FormatterEndToEndTest, DefineCrlfConverges) {
+  static constexpr FormatterTestCase kTestCases[] = {
+      {"`define A x.y\r\n"
+       "module m;\r\n"
+       "endmodule\r\n",
+       "`define A x.y\r\n"
+       "module m;\r\n"
+       "endmodule\r\n"},
+  };
+  FormatStyle style;
+  style.line_terminator = verible::LineTerminatorOptionStyle::kAuto;
+  RunFormatterTestCases(style, kTestCases);
+}
 }  // namespace
 }  // namespace formatter
 }  // namespace verilog
diff --git a/verible/verilog/formatting/formatter_test.cc b/verible/verilog/formatting/formatter_test.cc
index f26c999..aad3e60 100644
--- a/verible/verilog/formatting/formatter_test.cc
+++ b/verible/verilog/formatting/formatter_test.cc
@@ -128,22 +128,6 @@
   RunFormatterTestCases40(kSmokeFormatterTestCases);
 }
 
-// Regression for https://github.com/chipsalliance/verible/issues/2607:
-// A CRLF macro definition must keep a single line terminator so formatting
-// converges.
-TEST(FormatterEndToEndTest, DefineCrlfConverges) {
-  static constexpr std::string_view kInput =
-      "`define A x.y\r\n"
-      "module m;\r\n"
-      "endmodule\r\n";
-  FormatStyle style;
-  style.line_terminator = verible::LineTerminatorOptionStyle::kAuto;
-  std::ostringstream stream;
-  const auto status = FormatVerilog(kInput, "<filename>", style, stream);
-  EXPECT_OK(status) << status.message();
-  EXPECT_EQ(stream.str(), kInput);
-}
-
 }  // namespace
 }  // namespace formatter
 }  // namespace verilog