)]}'
{
  "commit": "09ee00e5c0359ebefa37bcc629400235b5816a28",
  "tree": "464bee6c58a5bda1d3755e1d52b67b45fbb94733",
  "parents": [
    "ae6edd520860559870d3588d050fd45ae40b8c4e"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Mon Sep 14 12:57:09 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Mon Sep 14 12:57:09 2026 +0000"
  },
  "message": "Fix CRLF macro definitions retaining carriage returns.\n\nStrip both CRLF bytes from discontinued macro definition lines so the formatter emits one line terminator and converges. Fixes #2607.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b1f378884c87f58197c8ecd9203fc9a560320321",
      "old_mode": 33188,
      "old_path": "verible/verilog/parser/verilog-lexer_test.cc",
      "new_id": "e23b9117bab460a31963de63dabe28e61ca711d0",
      "new_mode": 33188,
      "new_path": "verible/verilog/parser/verilog-lexer_test.cc"
    },
    {
      "type": "modify",
      "old_id": "759fcc2b719912f5b7b8509ea433688f281694e5",
      "old_mode": 33188,
      "old_path": "verible/verilog/parser/verilog.lex",
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      "new_mode": 33188,
      "new_path": "verible/verilog/parser/verilog.lex"
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}