)]}'
{
  "commit": "0e7dbcc1c45e000f229cb7ad269d36c88ada48ac",
  "tree": "dd88f59803bd4552afe6a13f0ac7e4abbdbcbc3a",
  "parents": [
    "e7017a1b341d44547fbcc54fe82458ea0baf3e67"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Tue Aug 18 00:12:01 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Tue Aug 18 00:12:01 2026 +0000"
  },
  "message": "Remove unused formatter BUILD deps after include cleanup\n\niterator-range and absl core_headers are unused after the #2542\nrefactor dropped make_range and ABSL_FALLTHROUGH_INTENDED.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "615059423e56ad5548d3924a1091a4857ecf68ef",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/BUILD",
      "new_id": "6431226d057c3cfb98074125670e9bcece8032af",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/BUILD"
    }
  ]
}