)]}'
{
  "id": "13bb1e3e6cea0465076ffab9fe99ea268f3e5a6a",
  "repo": "third_party/verible",
  "revision": "16d54aa72c6b73c1c336e2f918b9f2c643dc01ce",
  "path": "verilog/CST/expression.h"
}
