)]}'
{
  "id": "89f9f2435772ac4cda25e78f32ea67a00d3213a9",
  "repo": "third_party/verible",
  "revision": "1b2b9e5c1f01ada7b5dbd1d73ff181052c77d527",
  "path": "verilog/tools/lint/testdata/plusarg_assignment.sv"
}
