diff --git a/verible/common/formatting/align.cc b/verible/common/formatting/align.cc
index 74bc432..9f77014 100644
--- a/verible/common/formatting/align.cc
+++ b/verible/common/formatting/align.cc
@@ -1001,6 +1001,20 @@
       auto &line = node.Value();
       auto ftokens = line.TokensRange();
 
+      // Leading non-tree tokens before a forced wrap must stay on their own
+      // line. Putting them in a kInline prolog cell would glue e.g. `//\` onto
+      // the following `input` (GitHub issue 2539). Preserve original spacing
+      // for the whole row instead. Master's scanner already omits those
+      // leading tokens from column bids; this keeps ApplyAlignment from
+      // still inlining them.
+      if (align_actions.front().ftoken != ftokens.begin() &&
+          align_actions.front().ftoken->before.break_decision ==
+              SpacingOptions::kMustWrap) {
+        FormatUsingOriginalSpacing(TokenPartitionRange(*row, std::next(*row)));
+        ++row;
+        continue;
+      }
+
       line.SetPartitionPolicy(PartitionPolicyEnum::kAlreadyFormatted);
 
       verible::TokenPartitionTree *current_cell = nullptr;
diff --git a/verible/verilog/formatting/align.cc b/verible/verilog/formatting/align.cc
index 6640adb..24696c7 100644
--- a/verible/verilog/formatting/align.cc
+++ b/verible/verilog/formatting/align.cc
@@ -147,6 +147,32 @@
          b == AlignmentGroupBoundary::kBlankLinesAndSeparatorComments;
 }
 
+// True when non-tree tokens (e.g. // comments, line-continuation `\`) precede
+// the origin, and the first origin token must start a new line. Aligning such
+// partitions would glue the leading tokens onto the origin line via kInline
+// cells (GitHub issue 2539). Leave them out of alignment instead.
+static bool PartitionHasLeadingTokensBeforeForcedWrap(
+    const TokenPartitionTree &partition) {
+  const auto &uwline = partition.Value();
+  const verible::Symbol *origin = uwline.Origin();
+  if (origin == nullptr) return false;
+
+  const auto ftokens = uwline.TokensRange();
+  if (ftokens.empty()) return false;
+
+  const verible::SyntaxTreeLeaf *first_leaf = verible::GetLeftmostLeaf(*origin);
+  if (first_leaf == nullptr) return false;
+
+  const verible::TokenInfo &first_tree_token = first_leaf->get();
+  auto ftoken_it = ftokens.begin();
+  while (ftoken_it != ftokens.end() &&
+         *(ftoken_it->token) != first_tree_token) {
+    ++ftoken_it;
+  }
+  if (ftoken_it == ftokens.begin() || ftoken_it == ftokens.end()) return false;
+  return ftoken_it->before.break_decision == verible::SpacingOptions::kMustWrap;
+}
+
 static bool IgnoreCommentsAndPreprocessingDirectives(
     const TokenPartitionTree &partition) {
   const auto &uwline = partition.Value();
@@ -159,6 +185,8 @@
   // ignore lines containing only comments
   if (TokensAreAllCommentsOrAttributes(token_range)) return true;
 
+  if (PartitionHasLeadingTokensBeforeForcedWrap(partition)) return true;
+
   // ignore partitions belonging to preprocessing directives
   return IsPreprocessorKeyword(
       verilog_tokentype(token_range.front().TokenEnum()));
@@ -199,6 +227,8 @@
     return true;
   }
 
+  if (PartitionHasLeadingTokensBeforeForcedWrap(partition)) return true;
+
   // ignore nested structs/unions
   if (verible::FindFirstSubtree(
           partition.Value().Origin(), [](const Symbol &symbol) {
diff --git a/verible/verilog/formatting/formatter_issue_regression_test.cc b/verible/verilog/formatting/formatter_issue_regression_test.cc
index 8f1fcef..9490a88 100644
--- a/verible/verilog/formatting/formatter_issue_regression_test.cc
+++ b/verible/verilog/formatting/formatter_issue_regression_test.cc
@@ -314,6 +314,28 @@
     EXPECT_EQ(stream.str(), test_case.expected) << "code:\n" << test_case.input;
   }
 }
+
+// Regression for https://github.com/chipsalliance/verible/issues/2539:
+// A // comment followed by a line-continuation `\` before aligned ports must
+// not abort in align.h, and must keep the comment on its own line.
+TEST(FormatterEndToEndTest, PortListCommentWithLineContinuationDoesNotAbort) {
+  static constexpr FormatterTestCase kTestCases[] = {
+      {"module m (\n"
+       "//\\\n"
+       "input a\n"
+       ",input b\n"
+       ");\n"
+       "endmodule\n",
+       "module m (\n"
+       "    //\\\n"
+       "        input a\n"
+       "    , input b\n"
+       ");\n"
+       "endmodule\n"},
+  };
+  FormatStyle style;  // default column_limit (100)
+  RunFormatterTestCases(style, kTestCases);
+}
 }  // namespace
 }  // namespace formatter
 }  // namespace verilog