)]}'
{
  "id": "b8b472878f56519dc1f18f2a01a65fe159c68570",
  "repo": "third_party/verible",
  "revision": "1ff4cd03addcbb4bbfa47990bd46bf0f84b8b9de",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.cc"
}