)]}'
{
  "commit": "26830d89f1dd2bd7a0d729932ae9a4f11d427449",
  "tree": "164c2c2d7ac502216795f10efc3da5ef855b790b",
  "parents": [
    "538c21a839f5b72cf3379776640f2bb14aa47eeb"
  ],
  "author": {
    "name": "hzeller",
    "email": "h.zeller@acm.org",
    "time": "Tue Sep 01 18:22:56 2026 +0000"
  },
  "committer": {
    "name": "hzeller",
    "email": "h.zeller@acm.org",
    "time": "Tue Sep 01 18:22:56 2026 +0000"
  },
  "message": "Deploying to gh-pages from @ chipsalliance/verible@6cce8f192b55640ddd5221b926cc952d979aa2b7 🚀\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "424de29e4227cf8730888b832cfc3c09d0a56bf0",
      "old_mode": 33188,
      "old_path": "index.md",
      "new_id": "43f7feada6dd4f460d5a13804c9fa3f90808f8a7",
      "new_mode": 33188,
      "new_path": "index.md"
    },
    {
      "type": "modify",
      "old_id": "5e41c6c70d6079da5de8ceb8a81001d2e8add716",
      "old_mode": 33188,
      "old_path": "lint.md",
      "new_id": "9a2c7685cf8b0a62804f527f8ce95b224906fc44",
      "new_mode": 33188,
      "new_path": "lint.md"
    },
    {
      "type": "modify",
      "old_id": "21191b6ea4c8d25d2f55ee036777df52d1271518",
      "old_mode": 33188,
      "old_path": "verilog_format.md",
      "new_id": "6b7cb0c4f26fb81789ccc8034bd9855ca5ee187a",
      "new_mode": 33188,
      "new_path": "verilog_format.md"
    },
    {
      "type": "modify",
      "old_id": "0b38a96d348e9d8aaf4468a796a2eeef49e4eb5a",
      "old_mode": 33188,
      "old_path": "verilog_lint.md",
      "new_id": "c577ca319ced1910537af66850860cbe597e6f65",
      "new_mode": 33188,
      "new_path": "verilog_lint.md"
    },
    {
      "type": "modify",
      "old_id": "13cfc2e2768cabdd2ab80869b0ec3c60265ea837",
      "old_mode": 33188,
      "old_path": "verilog_syntax.md",
      "new_id": "5b41f29b5a7f679a2074ddf2faeafba182ccc9f5",
      "new_mode": 33188,
      "new_path": "verilog_syntax.md"
    }
  ]
}