)]}'
{
  "commit": "41a1e24f64a31e387ef0fbd0098259950e597e09",
  "tree": "75a87ea67bdbc7d6d742139e02a6bfa15baf1bcc",
  "parents": [
    "d591c89ca1aea936f6479ee7c25286b13e4c7dc1"
  ],
  "author": {
    "name": "Mateusz Sierszulski",
    "email": "msierszulski@antmicro.com",
    "time": "Tue Dec 06 13:32:27 2022 +0100"
  },
  "committer": {
    "name": "Mateusz Sierszulski",
    "email": "msierszulski@antmicro.com",
    "time": "Tue Dec 06 13:32:27 2022 +0100"
  },
  "message": "Add unit test for calling system functions without parentheses\n\nSigned-off-by: Mateusz Sierszulski \u003cmsierszulski@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b0cf132d1a5d236bece23bd937e855b43c83d984",
      "old_mode": 33188,
      "old_path": "verilog/formatting/formatter_test.cc",
      "new_id": "8f00b0a7fb88eccae6eb8c01b79b02c9e7f6f610",
      "new_mode": 33188,
      "new_path": "verilog/formatting/formatter_test.cc"
    }
  ]
}