)]}'
{
  "commit": "42b49fc973a87570e95e7c99e17c46fda8f28dee",
  "tree": "755a6cc86df0f04528b30c5681ab3b23fb9c627e",
  "parents": [
    "992e939077935fb5f294dbc3e88c4dc6670f75ef"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Thu Sep 17 15:02:44 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Thu Sep 17 15:02:44 2026 +0000"
  },
  "message": "Fixed clang tidy\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3775053e8d2a90fc528ee0ed56fa68b196bbe037",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/formatter_issue_regression_test.cc",
      "new_id": "4434bab4c8be2ca552978f391b66e3c240d3dee0",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/formatter_issue_regression_test.cc"
    }
  ]
}