)]}'
{
  "commit": "43fa33b285338db1465c03fea5d42d7502f88862",
  "tree": "4f07718ba1794292076db87c2ef32c79e725e960",
  "parents": [
    "03f69da11155755ca3b28bc9c0c1a4fd6dd5897d"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Thu Sep 17 15:09:31 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Thu Sep 17 15:09:31 2026 +0000"
  },
  "message": "Fixed clang-tidy\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b952cd9abbb83e4f4cc16085925f21eb7c5ff1c0",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/formatter_issue_regression_test.cc",
      "new_id": "550dd38b9aa5dcf384a1be11655b2fd72b570f39",
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}