)]}'
{
  "commit": "4441d9b359788f2a542291103144ba0848ed8c32",
  "tree": "d04644076c2f6c3dcea28b6273e8c0efedd4d3f8",
  "parents": [
    "9292855870987559d0c9836bf7d057e96e249c91",
    "075abd338696361c8be83c8dfa024f48d63f7207"
  ],
  "author": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Tue Nov 15 08:22:25 2022 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Nov 15 08:22:25 2022 -0800"
  },
  "message": "Merge pull request #1528 from karimtera/preprocessor_whitespace\n\nSupport whitespaces in VerilogPreprocess",
  "tree_diff": []
}