)]}'
{
  "commit": "4dbf5b407ee6f61339146374f6741c3e1fe446f4",
  "tree": "e2b6655c60b015b8f52f3fec8b67e784a582c2bc",
  "parents": [
    "14e75c386bf5e731e7c5ea7cc3581939230cf7dc"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Mon Aug 17 20:49:01 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Mon Aug 17 20:49:01 2026 +0000"
  },
  "message": "Created new function AreSpellingEqualLineEndingMacros\n\nCreated common location for checking macro against line ending.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "026c197cf257c99b38b77c5c88cf4d81cbcc2fed",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/verilog-equivalence.cc",
      "new_id": "68c8c980d247986bd19b067ac38c39eea5ef7238",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/verilog-equivalence.cc"
    }
  ]
}