)]}'
{
  "commit": "4f9313d4d0faa8b04e409f4f425830fe6dbb85a5",
  "tree": "04ad29eed9fa370391d880fb5c2b34e0fca816d2",
  "parents": [
    "68343073a71e577103bcc89cb89a4b3fd592f986"
  ],
  "author": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Tue Jun 03 22:49:43 2025 +0200"
  },
  "committer": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Wed Jun 04 18:33:40 2025 +0200"
  },
  "message": "Provide an \u0027auto\u0027 option for --line_terminator\n\nIf \u0027auto\u0027 is chosen, output CRLF line endings if more than 50% of the\ninput is CRLF, otherwise LF.\n\nThe other choices, CRLF or LF, behave as before.\n\nNB: The default changes with this change: previously, we always\nconverted a CRLF input to LF, now the default is \u0027auto\u0027\n\nIssues: #2424 #2370\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ab8474548f59f5f0211fc60695dfce2168e8c5d6",
      "old_mode": 33188,
      "old_path": "verible/common/formatting/basic-format-style-init.cc",
      "new_id": "c3b74f282f7a8850b34483a4c6ff19e7e70a4fcc",
      "new_mode": 33188,
      "new_path": "verible/common/formatting/basic-format-style-init.cc"
    },
    {
      "type": "modify",
      "old_id": "9cc5d4588f35abc3ebb2070e46560aa148bf8d88",
      "old_mode": 33188,
      "old_path": "verible/common/formatting/basic-format-style.cc",
      "new_id": "6c693a50928537040605fd166c1336f3017b1e8e",
      "new_mode": 33188,
      "new_path": "verible/common/formatting/basic-format-style.cc"
    },
    {
      "type": "modify",
      "old_id": "f01825ca7e21e43e5813715ddf922eaa27dff801",
      "old_mode": 33188,
      "old_path": "verible/common/formatting/basic-format-style.h",
      "new_id": "8228f7ced2c4f160eb0039099d3726ab1e4df3da",
      "new_mode": 33188,
      "new_path": "verible/common/formatting/basic-format-style.h"
    },
    {
      "type": "modify",
      "old_id": "0195bb8b16af7221bd9f33ac847bfdf09ea64280",
      "old_mode": 33188,
      "old_path": "verible/common/text/BUILD",
      "new_id": "d70a016c97ea8333a623919672308373aa0bc7d9",
      "new_mode": 33188,
      "new_path": "verible/common/text/BUILD"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0876e40d41b6b4a7dedbc5f0d937b054cf1aa6f0",
      "new_mode": 33188,
      "new_path": "verible/common/text/line-terminator.cc"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "52ab678cceaaf93e7358c6869fddd9d9ba230e1a",
      "new_mode": 33188,
      "new_path": "verible/common/text/line-terminator.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ff480a285e95527274312fab1a9c129c0005fb47",
      "new_mode": 33188,
      "new_path": "verible/common/text/line-terminator_test.cc"
    },
    {
      "type": "modify",
      "old_id": "929e59213bb444a54529e8a2f5e2ce26a9b8dd66",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/BUILD",
      "new_id": "e22d705d467c99c70022c6b73014a6fc1068ce6a",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/BUILD"
    },
    {
      "type": "modify",
      "old_id": "4323c72cceeb39baeb2f33909c7ab8419277c281",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/comment-controls.cc",
      "new_id": "df9c5830139c9368e9dff98d2e5dee0e128afb48",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/comment-controls.cc"
    },
    {
      "type": "modify",
      "old_id": "edfcac1cd5e8f00d7a1d54e09dd60b824e9272f0",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/comment-controls.h",
      "new_id": "fa40e40e5b243ac2b4f89c712f0cb0c3d7932e8e",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/comment-controls.h"
    },
    {
      "type": "modify",
      "old_id": "2a3bbd598ca08db80a7645eaf5f48cbe813261a8",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/comment-controls_test.cc",
      "new_id": "1e4c8d757369c105a634e69188a547e5c81d0f47",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/comment-controls_test.cc"
    },
    {
      "type": "modify",
      "old_id": "e0ee77e4bb6980ed5e4b30aadddbcbc980a8b54a",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/formatter.cc",
      "new_id": "34c7d37a8d04f0f4df208d580b704cb1f82155b3",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/formatter.cc"
    },
    {
      "type": "modify",
      "old_id": "f0acb311227faa1b9cf3dd649320e03286700d4d",
      "old_mode": 33188,
      "old_path": "verible/verilog/tools/formatter/README.md",
      "new_id": "b9d167d8acff838ccda496b6d95355165317ac53",
      "new_mode": 33188,
      "new_path": "verible/verilog/tools/formatter/README.md"
    },
    {
      "type": "modify",
      "old_id": "e5c8b7c14f5626f10bd46618cd19c7018de583f9",
      "old_mode": 33261,
      "old_path": "verible/verilog/tools/formatter/format_line_terminator_test.sh",
      "new_id": "a41caea1c0da44db736c9bba6e57cd81b6e367e5",
      "new_mode": 33261,
      "new_path": "verible/verilog/tools/formatter/format_line_terminator_test.sh"
    }
  ]
}