)]}'
{
  "commit": "5201cfa1030909e282087bf81c937c72c98f9391",
  "tree": "ad188985493762ab4f7987ead0aae8a40442b1e9",
  "parents": [
    "fd02cb426a323faa6c68f3237de8b44620407cb3"
  ],
  "author": {
    "name": "MinaToma",
    "email": "minatoma1999@gmail.com",
    "time": "Tue Sep 15 14:31:52 2020 -0700"
  },
  "committer": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Tue Sep 15 16:16:11 2020 -0700"
  },
  "message": "PR #447: Module port data type forwarding\nFixes #419\n\nGitHub PR https://github.com/google/verible/pull/447\n\nCopybara import of the project:\n\n  - 92798399785eeb230894e1b967a78bcc5e77e67a Propagating Port Type in Module by MinaToma \u003cminatoma1999@gmail.com\u003e\n  - 55a9364fe71c02c39ce462afbde6bf886707a563 More Tests for Port Data Type Forwarding in Modules by MinaToma \u003cminatoma1999@gmail.com\u003e\n  - 94c9da0a480d1c6ce0b9a0a31a8128787b4995d5 More Tests by MinaToma \u003cminatoma1999@gmail.com\u003e\n\nCloses #447\n\nPiperOrigin-RevId: 331856863\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8eebfcd52c52b41e9696a93fd2af560fe5730cd6",
      "old_mode": 33188,
      "old_path": "verilog/CST/port.cc",
      "new_id": "bab8765c106c7ba7f2357fe490637cfd361f63c7",
      "new_mode": 33188,
      "new_path": "verilog/CST/port.cc"
    },
    {
      "type": "modify",
      "old_id": "d8827d7490eb9b33cdc1dd32dc859bbe8ecca8f6",
      "old_mode": 33188,
      "old_path": "verilog/CST/port.h",
      "new_id": "ce11eafef6e5208fedf10fdeb35f1b56c9a7c2de",
      "new_mode": 33188,
      "new_path": "verilog/CST/port.h"
    },
    {
      "type": "modify",
      "old_id": "550536459b5f5192d284849ad86e4b9688f637d3",
      "old_mode": 33188,
      "old_path": "verilog/CST/port_test.cc",
      "new_id": "8168378167bc569538ec8a55df2f8f699e7402ea",
      "new_mode": 33188,
      "new_path": "verilog/CST/port_test.cc"
    },
    {
      "type": "modify",
      "old_id": "28f23aaa0e3108e981546655185a211bc5fb3046",
      "old_mode": 33188,
      "old_path": "verilog/tools/kythe/indexing_facts_tree_extractor.cc",
      "new_id": "1198279fb10a9116f601cd9bf43693cf691d92de",
      "new_mode": 33188,
      "new_path": "verilog/tools/kythe/indexing_facts_tree_extractor.cc"
    },
    {
      "type": "modify",
      "old_id": "3184a1f03dc88dff9ae068a27c589a1f174e4059",
      "old_mode": 33188,
      "old_path": "verilog/tools/kythe/indexing_facts_tree_extractor.h",
      "new_id": "ffd3ad5ac7f3583f3ad0593988b1f39cbbf6c10f",
      "new_mode": 33188,
      "new_path": "verilog/tools/kythe/indexing_facts_tree_extractor.h"
    },
    {
      "type": "modify",
      "old_id": "968d57f0ab35b538b148378f428a3f8edcc9d15c",
      "old_mode": 33188,
      "old_path": "verilog/tools/kythe/indexing_facts_tree_extractor_test.cc",
      "new_id": "be77c696d29aa69fbacccc62514ed29bbef73983",
      "new_mode": 33188,
      "new_path": "verilog/tools/kythe/indexing_facts_tree_extractor_test.cc"
    }
  ]
}