)]}'
{
  "commit": "5fe7f29b0316436f17ae49a3b726d36b17d858fc",
  "tree": "0e6fea6866f81375eafbd072616876edece54893",
  "parents": [
    "f5e04028779cf65dc52d9f74eb2fc3895ae5c682"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Mon Sep 14 12:41:38 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Mon Sep 14 12:41:38 2026 +0000"
  },
  "message": "Updated formatting\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cc18f987674e8b469b301f6cc7e7d83114d3d6e0",
      "old_mode": 33188,
      "old_path": "verible/verilog/parser/verilog-lexer_test.cc",
      "new_id": "23d8cdaa8d2dfb3949a18b8d8f5bfc400ea2d6d0",
      "new_mode": 33188,
      "new_path": "verible/verilog/parser/verilog-lexer_test.cc"
    }
  ]
}