)]}'
{
  "commit": "61d8d5f2cc4a92ec8f84d5facc19e9742f05c9b0",
  "tree": "b2df2670f1aab6fdad5ec43e1c938f56707f9fcc",
  "parents": [
    "b59898d8c95712d56779f3340622517c3fee6beb"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Sun Jul 19 18:50:22 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Sun Jul 19 18:50:22 2026 +0000"
  },
  "message": "Fixed formatting from clang-tidy\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "80ec58d61b937cb665a286201bca7b93a08142ef",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/formatter.cc",
      "new_id": "8384befb9ee7eb2458172b46c9420b2a2b5eca49",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/formatter.cc"
    }
  ]
}