)]}'
{
  "id": "487cc596b00369fe0fb7d7f218ad491ab7a55dc5",
  "repo": "third_party/verible",
  "revision": "6dcf93b43022a2d8a73c051339d0877bb95ffc55",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.cc"
}