)]}'
{
  "id": "ab5c576e227d14e9894ef69f46e02cd16ebbb15e",
  "repo": "third_party/verible",
  "revision": "74eb33db7dbb45791f4902023afdcd456b9bb73a",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.h"
}