)]}'
{
  "id": "487cc596b00369fe0fb7d7f218ad491ab7a55dc5",
  "repo": "third_party/verible",
  "revision": "7eb836276c29ec86993b1f67ef577d5512f2ca02",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.cc"
}