The language server provides a couple of features from the Verible SystemVerilog productivity suite right in the editor.
/*AUTO...*/ pragmas in Verilog and SystemVerilog code. These expansions are available as code actions.AUTOARG – generates a list of non-ANSI ports in a module header,AUTOINST with AUTO_TEMPLATE – generates connections in a module instance based on the instantiated module's ports,AUTOINPUT, AUTOOUTPUT, AUTOINOUT – declares ports based on connections generated by AUTOINST,AUTOWIRE – declares wires based on connections generated by AUTOINST,AUTOREG – declares regs for outputs not connected to any module instance.The Verible plug-in needs the verible-verilog-ls executable installed on your machine.
On Linux and Windows, the plug-in will try to download the necessary executable (if it's not already available).
Get a binary distribution for your Operating System at https://github.com/chipsalliance/verible/releases
Alternatively, build Verible from source.
File bugs on the public github issue tracker. Provide (sanitized) code examples if needed to illustrate an issue.