)]}'
{
  "commit": "872b2e462d077c0382e755b73dee7fbabd57394d",
  "tree": "1c60b51c6a3929d2e2a0c43786c2e8b6e6b503fd",
  "parents": [
    "63f00dd819e1369fe1a86c991ccb65961e846e12"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Thu Dec 21 14:51:05 2023 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Thu Dec 21 14:51:05 2023 +0000"
  },
  "message": "Fixed variable name\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7b30fcda8f00975deb143301bd9b5e46a66bb78a",
      "old_mode": 33188,
      "old_path": "verilog/tools/formatter/verilog_format.cc",
      "new_id": "170cdf70cb7db9ac674963395f16c8e626ffe7e5",
      "new_mode": 33188,
      "new_path": "verilog/tools/formatter/verilog_format.cc"
    }
  ]
}