)]}'
{
  "id": "13bb1e3e6cea0465076ffab9fe99ea268f3e5a6a",
  "repo": "third_party/verible",
  "revision": "876c18b0d6f2dd6d476e3f728315260b90b01a5c",
  "path": "verilog/CST/expression.h"
}