)]}'
{
  "commit": "9afca2df0a141dd096bbf8f46a0f13ab35278090",
  "tree": "fe66148470da5530f46fd986202aeae5cd9cdee1",
  "parents": [
    "70872676a3ec7a7fbaefacead376392e39ad4b3e"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue Jun 01 15:25:50 2021 +0200"
  },
  "committer": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue Jun 01 15:25:50 2021 +0200"
  },
  "message": "Add a switch to force coverpoint expansion\n\nSigned-off-by: Rafal Kapuscik \u003crkapuscik@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "495caa6d271143dec95d3810c614fe822a39b79a",
      "old_mode": 33188,
      "old_path": "verilog/formatting/format_style.h",
      "new_id": "f230a06cdacb9ab3f2f7fb1d8b12412fba1921ab",
      "new_mode": 33188,
      "new_path": "verilog/formatting/format_style.h"
    },
    {
      "type": "modify",
      "old_id": "b43a1b3ec9d7c9aa6dc64029b20c7c6abf59bd03",
      "old_mode": 33188,
      "old_path": "verilog/tools/formatter/verilog_format.cc",
      "new_id": "7032b5352010875392b2b347a5e6f8000e1cef27",
      "new_mode": 33188,
      "new_path": "verilog/tools/formatter/verilog_format.cc"
    }
  ]
}