)]}'
{
  "id": "487cc596b00369fe0fb7d7f218ad491ab7a55dc5",
  "repo": "third_party/verible",
  "revision": "a3feb9b5e31b2a454af8200fd5c1dbd36a141ec8",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.cc"
}