)]}'
{
  "id": "89f9f2435772ac4cda25e78f32ea67a00d3213a9",
  "repo": "third_party/verible",
  "revision": "a3feb9b5e31b2a454af8200fd5c1dbd36a141ec8",
  "path": "verilog/tools/lint/testdata/plusarg_assignment.sv"
}