)]}'
{
  "id": "ab5c576e227d14e9894ef69f46e02cd16ebbb15e",
  "repo": "third_party/verible",
  "revision": "aa0c1af6ca93c75457fe7c41c247e4ddd3447fe3",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.h"
}