)]}'
{
  "commit": "ac1119bf707d15457619551a0e18bfc9ce1f443c",
  "tree": "750b415b5d12de554da21ded15d51bfd8c367332",
  "parents": [
    "d122fac8c990ff25b8ecbced33965c0cc8bc3ab5"
  ],
  "author": {
    "name": "Jan Bylicki",
    "email": "jbylicki@antmicro.com",
    "time": "Wed Dec 14 14:46:54 2022 +0100"
  },
  "committer": {
    "name": "Jan Bylicki",
    "email": "jbylicki@antmicro.com",
    "time": "Wed Dec 14 15:50:58 2022 +0100"
  },
  "message": "verilog: formatting: formatter_test.cc: Added port list formatting test\n\nAdded the test case for the formatter port list multi-line\ncomment formatting\n\nSigned-off-by: Jan Bylicki \u003cjbylicki@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b0cf132d1a5d236bece23bd937e855b43c83d984",
      "old_mode": 33188,
      "old_path": "verilog/formatting/formatter_test.cc",
      "new_id": "1dd3b592ba025f1e0da201e170cc9d5ea6ba3620",
      "new_mode": 33188,
      "new_path": "verilog/formatting/formatter_test.cc"
    }
  ]
}