)]}'
{
  "commit": "b41588edb5262b7b2cd3be411d05069b8892113b",
  "tree": "28d07a8f175fd475bc07cf27f329c43113fbc18b",
  "parents": [
    "93adb37c0ddd0e5862c3e4341d0b0e9a31ec08af"
  ],
  "author": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Sat May 31 12:41:27 2025 +0200"
  },
  "committer": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Sat May 31 16:11:19 2025 +0200"
  },
  "message": "Don\u0027t use down_cast\u003c\u003e with the assumption that type-mismatch returns null.\n\nWe typically don\u0027t compile-in RTTI so relying on down_cast\u003c\u003e returning\nnullptr or a correct type will result in subtle issues.\n\nInstead, provide MaybeNode() and MaybeLeaf() that use the SymbolKind\nto provide such casts.\n\nThis should be expanded:\n  * Ideally we remove _all_ uses of down_cast\u003c\u003e and use type-safe\n    ways of doing the same thing (and then: remove verible::down_cast\u003c\u003e).\n  * There are a few places where we CHECK() fail on type-mismatch, assuming\n    these can\u0027t happen; but that depends on how valid our syntax tree is,\n    which depends on the input the the parser to reject such input. These\n    should be reformulated with graceful error handling.\n\nFixes #2419\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d4a1715b625afd293558d6ef7dcd35d268f2b709",
      "old_mode": 33188,
      "old_path": "verible/common/analysis/matcher/BUILD",
      "new_id": "2d93eb90e53b182ca3eb826117f21163a9b674b6",
      "new_mode": 33188,
      "new_path": "verible/common/analysis/matcher/BUILD"
    },
    {
      "type": "modify",
      "old_id": "0feca1410cbe4a5c883cb2883e4341cd1e9d0066",
      "old_mode": 33188,
      "old_path": "verible/common/analysis/matcher/bound-symbol-manager.h",
      "new_id": "46ef0e4b8785db7ca2d84b409724715c1b2cd210",
      "new_mode": 33188,
      "new_path": "verible/common/analysis/matcher/bound-symbol-manager.h"
    },
    {
      "type": "modify",
      "old_id": "4a349daa35cd018290cc7476bf47340935ed3e9b",
      "old_mode": 33188,
      "old_path": "verible/common/text/symbol.h",
      "new_id": "ad8e95fe3d457baa8865558154ec8f377916da08",
      "new_mode": 33188,
      "new_path": "verible/common/text/symbol.h"
    },
    {
      "type": "modify",
      "old_id": "cadd313f9063633705386c646f319c5b1b401b32",
      "old_mode": 33188,
      "old_path": "verible/common/text/tree-utils.cc",
      "new_id": "b76be7b3a0b8f3b13701c6b2f13314dcf23f26ef",
      "new_mode": 33188,
      "new_path": "verible/common/text/tree-utils.cc"
    },
    {
      "type": "modify",
      "old_id": "8a18924d53f849e50398ebccf070bdac47eaf221",
      "old_mode": 33188,
      "old_path": "verible/common/text/tree-utils.h",
      "new_id": "475295bcf512c438fff0943310c63eb66afdb282",
      "new_mode": 33188,
      "new_path": "verible/common/text/tree-utils.h"
    },
    {
      "type": "modify",
      "old_id": "a2ecea29cb6125aebc9cc1afecb9c4d1b8305d03",
      "old_mode": 33188,
      "old_path": "verible/verilog/CST/BUILD",
      "new_id": "98f4c9b4ba98988733081052e4f2c9535816ec84",
      "new_mode": 33188,
      "new_path": "verible/verilog/CST/BUILD"
    },
    {
      "type": "modify",
      "old_id": "39d75de2e6538a871358832be69563bd13163bb9",
      "old_mode": 33188,
      "old_path": "verible/verilog/CST/expression.cc",
      "new_id": "72566266852091ee1f35c8a0f717888fb1f4d0e1",
      "new_mode": 33188,
      "new_path": "verible/verilog/CST/expression.cc"
    },
    {
      "type": "modify",
      "old_id": "e5adc8287699030a6cef07597869fefa5cc517fc",
      "old_mode": 33188,
      "old_path": "verible/verilog/CST/identifier.cc",
      "new_id": "9f03a0cae7a1e65131b54f9cb99cd2df2ca06330",
      "new_mode": 33188,
      "new_path": "verible/verilog/CST/identifier.cc"
    },
    {
      "type": "modify",
      "old_id": "00af7e6e21ef2ec7967a4bb83d61e19bb574cdfe",
      "old_mode": 33188,
      "old_path": "verible/verilog/CST/verilog-treebuilder-utils.cc",
      "new_id": "91eea0f5b1c6b2b9c693e7574b4331480de976cc",
      "new_mode": 33188,
      "new_path": "verible/verilog/CST/verilog-treebuilder-utils.cc"
    },
    {
      "type": "modify",
      "old_id": "98178d92cd169b20e457666a88bdf21140d72a90",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/BUILD",
      "new_id": "5ecdd2073fe4e7362687962cad1a68a624103074",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/BUILD"
    },
    {
      "type": "modify",
      "old_id": "0988b8daea551db96dafe7bd097afa4d391bede2",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/always-comb-blocking-rule.cc",
      "new_id": "68e050981ce43a4da6f95a092921ca56a7f2206a",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/always-comb-blocking-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "3b0a4db9616b6cea9a7da2bab547e176a9b68bc4",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/always-ff-non-blocking-rule.cc",
      "new_id": "4922c52bd4855a5f0e5533f3833d9d4dbdb3e9e1",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/always-ff-non-blocking-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "9e5fed95130933a3f0abe93e28cad0b2136d810e",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/create-object-name-match-rule.cc",
      "new_id": "cc014f4bfd4124f3ad34800c8349bc80f9375f67",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/create-object-name-match-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "e4031061d2524f69e80ac279fae8d2762667d93a",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/forbidden-macro-rule.cc",
      "new_id": "34c3da14c261c9567291409a9278705eeec87ef7",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/forbidden-macro-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "24d058060f2cd889e839788e5b7288d6c7c6eb08",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/forbidden-symbol-rule.cc",
      "new_id": "04558ead8cfdd70a42e45d61b8f2358a8caa7fa1",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/forbidden-symbol-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "1639ef222dff2b5756b4887f6a8218d4a59b693b",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/module-instantiation-rules.cc",
      "new_id": "9a850e51f6fe5d7c2e29773d12c01045819fb454",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/module-instantiation-rules.cc"
    },
    {
      "type": "modify",
      "old_id": "bcae10b285927b55433ceb146297bbd2d8b11b18",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/plusarg-assignment-rule.cc",
      "new_id": "cc027e612c572a95f72649607877760b6e02cd73",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/plusarg-assignment-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "8c241631ec462046496430c64c934e9ca2e639d1",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/truncated-numeric-literal-rule.cc",
      "new_id": "298bc6ca49680dddc850c16e5a3aba7db276f6cd",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/truncated-numeric-literal-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "2269fff1c2d2c27acc3eb9f65e9805b099ba8ecc",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/undersized-binary-literal-rule.cc",
      "new_id": "ffc7c67c57e91fd6899fc3cd371e1a9214c25282",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/undersized-binary-literal-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "ad7cd046f68efc19082d638984e4d2bb821b8bf9",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/v2001-generate-begin-rule.cc",
      "new_id": "8d4b63b007ff531784b9b306a31fd2e9aba82d32",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/v2001-generate-begin-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "724e682530c16c75879c20da68bbf0631c31653a",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/checkers/void-cast-rule.cc",
      "new_id": "9965d1d4e901c7409cf7580a8b3d81c7463bc41a",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/checkers/void-cast-rule.cc"
    },
    {
      "type": "modify",
      "old_id": "0940ef8fcca65100b429bb43a962fed7b6f03a69",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/BUILD",
      "new_id": "929e59213bb444a54529e8a2f5e2ce26a9b8dd66",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/BUILD"
    },
    {
      "type": "modify",
      "old_id": "de4cd897a6429bd80bda0a4e770bf9e8c768f097",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/align.cc",
      "new_id": "55d8952cc9f414489af8b9e344c59127bf926804",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/align.cc"
    }
  ]
}
