)]}'
{
  "id": "b8b472878f56519dc1f18f2a01a65fe159c68570",
  "repo": "third_party/verible",
  "revision": "b805ed80b42838281ebebe7cc05922bfcd67f925",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.cc"
}