)]}'
{
  "id": "86105ef7df39fc974e91d3a52e88286c913f4e02",
  "repo": "third_party/verible",
  "revision": "b895b01318ee9d0ebfa535f309ea14b79e462d18",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.h"
}