Merge branch 'chipsalliance:master' into feat/issue_2073
diff --git a/verible/verilog/formatting/formatter_test.cc b/verible/verilog/formatting/formatter_test.cc
index ba51802..b3915f1 100644
--- a/verible/verilog/formatting/formatter_test.cc
+++ b/verible/verilog/formatting/formatter_test.cc
@@ -601,6 +601,52 @@
{"`timescale 1ns/1ps\n", //
"`timescale 1ns / 1ps\n"},
+ // Multiple compiler directives should remain on separate lines
+ // (regression test for bug where they were merged onto one line)
+ {"`timescale 1 ps / 1 ps\n"
+ "`default_nettype none\n",
+ "`timescale 1 ps / 1 ps\n"
+ "`default_nettype none\n"},
+ {"`resetall\n"
+ "`timescale 1ns/1ps\n"
+ "`default_nettype wire\n",
+ "`resetall\n"
+ "`timescale 1ns / 1ps\n"
+ "`default_nettype wire\n"},
+ // Test with multiple different compiler directives
+ {"`resetall\n"
+ "`celldefine\n"
+ "`timescale 1ns/1ps\n"
+ "`default_nettype none\n",
+ "`resetall\n"
+ "`celldefine\n"
+ "`timescale 1ns / 1ps\n"
+ "`default_nettype none\n"},
+ // Test with compiler directives before module
+ {"`timescale 1ps/1ps\n"
+ "`default_nettype none\n"
+ "module foo;endmodule\n",
+ "`timescale 1ps / 1ps\n"
+ "`default_nettype none\n"
+ "module foo;\nendmodule\n"},
+ // Test with various compiler directives
+ {"`suppress_faults\n"
+ "`enable_portfaults\n"
+ "`delay_mode_distributed\n",
+ "`suppress_faults\n"
+ "`enable_portfaults\n"
+ "`delay_mode_distributed\n"},
+ {"`default_decay_time 10\n"
+ "`default_trireg_strength 50\n",
+ "`default_decay_time 10\n"
+ "`default_trireg_strength 50\n"},
+ {"`begin_keywords \"1800-2017\"\n"
+ "module test;endmodule\n"
+ "`end_keywords\n",
+ "`begin_keywords \"1800-2017\"\n"
+ "module test;\nendmodule\n"
+ "`end_keywords\n"},
+
// parameter test cases
{
" parameter int foo=0 ;",
diff --git a/verible/verilog/formatting/tree-unwrapper.cc b/verible/verilog/formatting/tree-unwrapper.cc
index 7198b9e..26b1ac6 100644
--- a/verible/verilog/formatting/tree-unwrapper.cc
+++ b/verible/verilog/formatting/tree-unwrapper.cc
@@ -782,7 +782,9 @@
case NodeEnum::kPreprocessorIfdefClause:
case NodeEnum::kPreprocessorIfndefClause:
case NodeEnum::kPreprocessorElseClause:
- case NodeEnum::kPreprocessorElsifClause: {
+ case NodeEnum::kPreprocessorElsifClause:
+ case NodeEnum::kTimescaleDirective:
+ case NodeEnum::kTopLevelDirective: {
VisitNewUnindentedUnwrappedLine(node);
break;
}
@@ -3200,6 +3202,16 @@
VLOG(4) << "handling preprocessor control flow token";
StartNewUnwrappedLine(PartitionPolicyEnum::kFitOnLineElseExpand, &leaf);
CurrentUnwrappedLine().SetIndentationSpaces(0);
+ } else if (IsPreprocessorKeyword(tag)) {
+ // Compiler directives (DR_* tokens) that don't have parent nodes
+ VLOG(4) << "handling compiler directive leaf token";
+ StartNewUnwrappedLine(PartitionPolicyEnum::kFitOnLineElseExpand, &leaf);
+ // Only unindent if at top level (context is empty) or inside preprocessor
+ // clauses
+ if (Context().empty() ||
+ IsPreprocessorClause(NodeEnum(Context().top().Tag().tag))) {
+ CurrentUnwrappedLine().SetIndentationSpaces(0);
+ }
} else if (IsEndKeyword(tag)) {
VLOG(4) << "handling end* keyword";
StartNewUnwrappedLine(PartitionPolicyEnum::kAlwaysExpand, &leaf);
diff --git a/verible/verilog/parser/verilog-token-classifications.cc b/verible/verilog/parser/verilog-token-classifications.cc
index a3c3523..27ab8ba 100644
--- a/verible/verilog/parser/verilog-token-classifications.cc
+++ b/verible/verilog/parser/verilog-token-classifications.cc
@@ -102,6 +102,30 @@
case verilog_tokentype::PP_elsif:
case verilog_tokentype::PP_endif:
case verilog_tokentype::PP_undef:
+ // Compiler directives (DR_*)
+ case verilog_tokentype::DR_timescale:
+ case verilog_tokentype::DR_resetall:
+ case verilog_tokentype::DR_celldefine:
+ case verilog_tokentype::DR_endcelldefine:
+ case verilog_tokentype::DR_unconnected_drive:
+ case verilog_tokentype::DR_nounconnected_drive:
+ case verilog_tokentype::DR_default_nettype:
+ case verilog_tokentype::DR_suppress_faults:
+ case verilog_tokentype::DR_nosuppress_faults:
+ case verilog_tokentype::DR_enable_portfaults:
+ case verilog_tokentype::DR_disable_portfaults:
+ case verilog_tokentype::DR_delay_mode_distributed:
+ case verilog_tokentype::DR_delay_mode_path:
+ case verilog_tokentype::DR_delay_mode_unit:
+ case verilog_tokentype::DR_delay_mode_zero:
+ case verilog_tokentype::DR_default_decay_time:
+ case verilog_tokentype::DR_default_trireg_strength:
+ case verilog_tokentype::DR_pragma:
+ case verilog_tokentype::DR_uselib:
+ case verilog_tokentype::DR_begin_keywords:
+ case verilog_tokentype::DR_end_keywords:
+ case verilog_tokentype::DR_protect:
+ case verilog_tokentype::DR_endprotect:
return true;
default:
return false;
