)]}'
{
  "commit": "bcdd57dd2a7f50843a1ad5afd4b543d2c7261578",
  "tree": "d02389e094560e4732f1dcd20c6d00b64044b00d",
  "parents": [
    "1ea007ec87b468595f95b40d095d09551b058b40"
  ],
  "author": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Tue Aug 18 01:30:50 2026 +0000"
  },
  "committer": {
    "name": "Kalen Brunham",
    "email": "kalen.brunham@intel.com",
    "time": "Tue Aug 18 01:30:50 2026 +0000"
  },
  "message": "Keep CST leaf order for non-ANSI wire signed ports\n\nModule body ports such as `input wire signed [15:0] sig1` put\n`signed` before `wire` in kDataType. The formatter walks CST order\nand CHECK-failed in the tree-unwrapper (issue #2008).\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "dce9f05efd697236099ae84b37d8d68d7096cbc7",
      "old_mode": 33188,
      "old_path": "verible/verilog/formatting/formatter_test.cc",
      "new_id": "45e1e775ce88546afce4b03e47d73ad3129dfe83",
      "new_mode": 33188,
      "new_path": "verible/verilog/formatting/formatter_test.cc"
    },
    {
      "type": "modify",
      "old_id": "f1c24a83b97f4c2cc030c9d21f3892721551a4d0",
      "old_mode": 33188,
      "old_path": "verible/verilog/parser/verilog.y",
      "new_id": "a6de1a84129f1a363cfd8fb45cf50cc270345d31",
      "new_mode": 33188,
      "new_path": "verible/verilog/parser/verilog.y"
    }
  ]
}