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name: lexer/parser issue about: Lexer and parser bugs title: '' labels: rejects-valid syntax assignees: ''

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Describe the bug

Short summary.

To Reproduce

// Test case (preferably reduced) that illustrates the problem.

Include any options used.

Actual behavior:

Did it reject valid code? or crash?

Expected behavior

A clear and concise description of what you expected to happen. Citations to the SystemVerilog-2017 Standard (LRM) would help.