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verible
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c428b43c153fa0708394d76824d00a0e94801683
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.
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verilog
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tools
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lint
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testdata
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legacy_genvar_declaration.sv
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// verilog_syntax: parse-as-module-body
genvar k
;
for
(
k
=
0
;
k
<
FooParam
;
k
++)
begin
:
gen_loop
// code
end
