)]}'
{
  "id": "487cc596b00369fe0fb7d7f218ad491ab7a55dc5",
  "repo": "third_party/verible",
  "revision": "c764102bc3f048cd8dc781f28b3d3dabfd17b855",
  "path": "verilog/analysis/checkers/plusarg_assignment_rule.cc"
}