)]}'
{
  "commit": "d6084ac77e62893a00425dd3eb166ae9b1a8388c",
  "tree": "e5c0956f6e787dc2c058c077c9dfb4de07dec70c",
  "parents": [
    "93b39665a0ad11a8c1395e56bea75a64dd52c53a"
  ],
  "author": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Sat Jun 06 22:52:05 2026 +0200"
  },
  "committer": {
    "name": "Henner Zeller",
    "email": "h.zeller@acm.org",
    "time": "Sat Jun 06 22:53:27 2026 +0200"
  },
  "message": "No need to optionally include vlog_is_on for old absl anymore.\n\nWe moved to a strictly newer version in the meantim.\n\nFixes #2336\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f04a440436e167d2c49c3d8588a6e71d88cef55a",
      "old_mode": 33188,
      "old_path": "verible/common/formatting/BUILD",
      "new_id": "48e6ac0271775822be52305c78a2f456ab06afc7",
      "new_mode": 33188,
      "new_path": "verible/common/formatting/BUILD"
    },
    {
      "type": "modify",
      "old_id": "145968781a8fe9c2c1a1d61c69edf86b1862a414",
      "old_mode": 33188,
      "old_path": "verible/common/formatting/layout-optimizer.cc",
      "new_id": "03eace9af1fe61c2e49a5f4b48365d6e11f6d80d",
      "new_mode": 33188,
      "new_path": "verible/common/formatting/layout-optimizer.cc"
    },
    {
      "type": "modify",
      "old_id": "5846df4a28005bf76f499262142b11a1e282fd2a",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/BUILD",
      "new_id": "ceac2189764d7ccb3f70cd79af770b40fdcf1afc",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/BUILD"
    },
    {
      "type": "modify",
      "old_id": "069d7696b37b692de97e7c31d24bc46d277c2ffe",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/verilog-analyzer.cc",
      "new_id": "7cb0d305147beebbcb59c27a0b5964c64c3f23b2",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/verilog-analyzer.cc"
    },
    {
      "type": "modify",
      "old_id": "bdc1fb078a5f2334ffe6a37242b68f0f326ee417",
      "old_mode": 33188,
      "old_path": "verible/verilog/analysis/verilog-linter.cc",
      "new_id": "1ca094e15658b25e54fd112301fe578eb4207232",
      "new_mode": 33188,
      "new_path": "verible/verilog/analysis/verilog-linter.cc"
    },
    {
      "type": "modify",
      "old_id": "2399f143df5222683f524d17daec659d6c8893d2",
      "old_mode": 33188,
      "old_path": "verible/verilog/tools/ls/BUILD",
      "new_id": "16b29313578c266db1fbd77dd5666199d06b9240",
      "new_mode": 33188,
      "new_path": "verible/verilog/tools/ls/BUILD"
    },
    {
      "type": "modify",
      "old_id": "3bc23edaa3c184a1b8a2372cb8dcd08df9256884",
      "old_mode": 33188,
      "old_path": "verible/verilog/tools/ls/symbol-table-handler.cc",
      "new_id": "2b67d271b28fe4dcf42fb39a5560523bb5ddcff0",
      "new_mode": 33188,
      "new_path": "verible/verilog/tools/ls/symbol-table-handler.cc"
    }
  ]
}
