Deploying to gh-pages from @ chipsalliance/verible@fb69b42d03392c734637576bb347a220b2e9c3ef 🚀
diff --git a/index.md b/index.md
index f1792cd..2abb31d 100644
--- a/index.md
+++ b/index.md
@@ -58,4 +58,4 @@
## Version
-Generated on 2025-06-04 00:01:30 +0200 from [d42da6b](https://github.com/google/verible/commit/d42da6b978d480222da00fb45ea5f84ec1158ab5)
+Generated on 2025-06-04 19:21:36 +0200 from [fb69b42](https://github.com/google/verible/commit/fb69b42d03392c734637576bb347a220b2e9c3ef)
diff --git a/lint.md b/lint.md
index f36f226..69e4f20 100644
--- a/lint.md
+++ b/lint.md
@@ -382,4 +382,4 @@
## Version
-Generated on 2025-06-04 00:01:30 +0200 from [d42da6b](https://github.com/google/verible/commit/d42da6b978d480222da00fb45ea5f84ec1158ab5)
+Generated on 2025-06-04 19:21:36 +0200 from [fb69b42](https://github.com/google/verible/commit/fb69b42d03392c734637576bb347a220b2e9c3ef)
diff --git a/verilog_format.md b/verilog_format.md
index fd1991e..d02f881 100644
--- a/verilog_format.md
+++ b/verilog_format.md
@@ -29,7 +29,9 @@
default: 2;
--line_break_penalty (Penalty added to solution for each introduced line
break.); default: 2;
- --line_terminator (Line terminator); default: LF;
+ --line_terminator (Line terminator. The 'auto' option chooses the output
+ depending on the observed input. The explicit choice CR or CRLF fixes the
+ output line terminator.); default: auto;
--over_column_limit_penalty (For penalty minimization, this represents the
baseline penalty value of exceeding the column limit. Additional penalty
of 1 is incurred for each character over this limit); default: 100;
@@ -130,4 +132,4 @@
## Version
-Generated on 2025-06-04 00:01:30 +0200 from [d42da6b](https://github.com/google/verible/commit/d42da6b978d480222da00fb45ea5f84ec1158ab5)
+Generated on 2025-06-04 19:21:36 +0200 from [fb69b42](https://github.com/google/verible/commit/fb69b42d03392c734637576bb347a220b2e9c3ef)
diff --git a/verilog_lint.md b/verilog_lint.md
index 0ebd120..67ff191 100644
--- a/verilog_lint.md
+++ b/verilog_lint.md
@@ -453,4 +453,4 @@
## Version
-Generated on 2025-06-04 00:01:30 +0200 from [d42da6b](https://github.com/google/verible/commit/d42da6b978d480222da00fb45ea5f84ec1158ab5)
+Generated on 2025-06-04 19:21:36 +0200 from [fb69b42](https://github.com/google/verible/commit/fb69b42d03392c734637576bb347a220b2e9c3ef)
diff --git a/verilog_syntax.md b/verilog_syntax.md
index 42ad7b4..9035fa0 100644
--- a/verilog_syntax.md
+++ b/verilog_syntax.md
@@ -51,4 +51,4 @@
## Version
-Generated on 2025-06-04 00:01:30 +0200 from [d42da6b](https://github.com/google/verible/commit/d42da6b978d480222da00fb45ea5f84ec1158ab5)
+Generated on 2025-06-04 19:21:36 +0200 from [fb69b42](https://github.com/google/verible/commit/fb69b42d03392c734637576bb347a220b2e9c3ef)
