PR #453: Initial Verifier Test
Fixes #395
Initial Kythe verification tests for SystermVerilog Kythe extractor.
GitHub PR https://github.com/google/verible/pull/453
Copybara import of the project:
- 3b4b86f6d350dc1adc0c52fbdb85eedc96763040 Initial Verifier Test by MinaToma <minatoma1999@gmail.com>
Closes #453
PiperOrigin-RevId: 331877297
diff --git a/verilog/tools/kythe/kythe_facts_extractor.cc b/verilog/tools/kythe/kythe_facts_extractor.cc
index 0b9f37d..70cd9f4 100644
--- a/verilog/tools/kythe/kythe_facts_extractor.cc
+++ b/verilog/tools/kythe/kythe_facts_extractor.cc
@@ -154,7 +154,12 @@
// Determines whether or not to create the childof relation with the parent.
switch (tag) {
case IndexingFactType::kFile:
- case IndexingFactType::kPackageImport: {
+ case IndexingFactType::kPackageImport:
+ case IndexingFactType::kVariableReference:
+ case IndexingFactType::kDataTypeReference:
+ case IndexingFactType::kMacroCall:
+ case IndexingFactType::kFunctionCall:
+ case IndexingFactType::kMacro: {
break;
}
default: {
@@ -173,7 +178,9 @@
case IndexingFactType::kModule:
case IndexingFactType::kModuleInstance:
case IndexingFactType::kVariableDefinition:
- case IndexingFactType::kFunctionOrTask: {
+ case IndexingFactType::kFunctionOrTask:
+ case IndexingFactType::kClass:
+ case IndexingFactType::kMacro: {
Visit(node, vname, current_scope);
break;
}
@@ -238,8 +245,8 @@
const auto& anchors = data_type_reference.Value().Anchors();
const Anchor& type = anchors[0];
- const VName type_vname = *ABSL_DIE_IF_NULL(
- scope_context_.SearchForDefinition(CreateModuleSignature(type.Value())));
+ const VName type_vname =
+ *ABSL_DIE_IF_NULL(scope_context_.SearchForDefinition(type.Value()));
const VName type_anchor = PrintAnchorVName(type);
GenerateEdgeString(type_anchor, kEdgeRef, type_vname);
@@ -284,7 +291,6 @@
GenerateFactString(variable_vname, kFactNodeKind, kNodeVariable);
GenerateFactString(variable_vname, kFactComplete, kCompleteDefinition);
-
GenerateEdgeString(variable_vname_anchor, kEdgeDefinesBinding,
variable_vname);
diff --git a/verilog/tools/kythe/testdata/more_testdata/class.sv b/verilog/tools/kythe/testdata/more_testdata/class.sv
new file mode 100644
index 0000000..286cc77
--- /dev/null
+++ b/verilog/tools/kythe/testdata/more_testdata/class.sv
@@ -0,0 +1,90 @@
+//- _FileNode.node/kind file
+
+//- @my_pkg defines/binding MyPkg
+//- MyPkg.node/kind package
+package my_pkg;
+
+ //- @my_class1 defines/binding MyClass1
+ //- MyClass1.node/kind record
+ //- MyClass1.complete definition
+ //- MyClass1 childof MyPkg
+ class my_class1;
+
+ //- @my_function defines/binding MyFunction
+ //- MyFunction.node/kind function
+ //- MyFunction.complete definition
+ //- MyFunction childof MyClass1
+ virtual function int my_function();
+ return 1;
+ endfunction
+
+ //- @my_task defines/binding MyTask
+ //- MyTask.node/kind function
+ //- MyTask.complete definition
+ //- MyTask childof MyClass1
+ task my_task();
+ $display(1);
+ endtask
+
+ //- @nested_class defines/binding NestedClass
+ //- NestedClass.node/kind record
+ //- NestedClass.complete definition
+ //- NestedClass childof MyClass1
+ class nested_class;
+ //- @nested_function defines/binding NestedFunction
+ //- NestedFunction.node/kind function
+ //- NestedFunction.complete definition
+ //- NestedFunction childof NestedClass
+ function int nested_function();
+ return 1;
+ endfunction
+ endclass
+
+ //- @my_class1 ref MyClass1
+ endclass : my_class1
+
+ //- @my_pkg ref MyPkg
+endpackage : my_pkg
+
+//- @my_module defines/binding MyModule
+//- MyModule.node/kind record
+//- MyModule.subkind module
+//- MyModule.complete definition
+module my_module;
+ //- @my_pkg ref/imports MyPkg
+ import my_pkg::*;
+ initial begin
+ //- @my_class1 ref MyClass1
+ //- @handle1 defines/binding Handle1
+ //- Handle1.node/kind variable
+ //- Handle1.complete definition
+ //- Handle1 childof MyModule
+ static my_class1 handle1 = new();
+
+ //- @my_class1 ref MyClass1
+ //- @handle3 defines/binding Handle3
+ //- Handle3.node/kind variable
+ //- Handle3.complete definition
+ //- Handle3 childof MyModule
+ //- @handle4 defines/binding Handle4
+ //- Handle4.node/kind variable
+ //- Handle4.complete definition
+ //- Handle4 childof MyModule
+ my_class1 handle3 = new(), handle4 = new();
+ end
+
+ //- @my_class3 defines/binding MyClass3
+ //- MyClass3.node/kind record
+ //- MyClass3.complete definition
+ //- MyClass3 childof MyModule
+ class my_class3;
+ //- @my_function3 defines/binding MyFunction3
+ //- MyFunction3.node/kind function
+ //- MyFunction3.complete definition
+ //- MyFunction3 childof MyClass3
+ function int my_function3();
+ return 1;
+ endfunction
+ //- @my_class3 ref MyClass3
+ endclass : my_class3
+endmodule
diff --git a/verilog/tools/kythe/testdata/more_testdata/function_and_task.sv b/verilog/tools/kythe/testdata/more_testdata/function_and_task.sv
new file mode 100644
index 0000000..043d3c7
--- /dev/null
+++ b/verilog/tools/kythe/testdata/more_testdata/function_and_task.sv
@@ -0,0 +1,42 @@
+//- _FileNode.node/kind file
+
+//- @my_function defines/binding MyFunction
+//- MyFunction.node/kind function
+//- MyFunction.complete definition
+//- @my_arg1 defines/binding MyArg1
+//- MyArg1.node/kind variable
+//- MyArg1.complete definition
+//- MyArg1 childof MyFunction
+//- @my_arg2 defines/binding MyArg2
+//- MyArg2.node/kind variable
+//- MyArg2.complete definition
+//- MyArg2 childof MyFunction
+function int my_function(int my_arg1, int my_arg2);
+ return 1;
+endfunction
+
+//- @my_task defines/binding MyTask
+//- MyFunction.node/kind function
+//- MyFunction.complete definition
+//- @my_arg3 defines/binding MyArg3
+//- MyArg3.node/kind variable
+//- MyArg3.complete definition
+//- MyArg3 childof MyTask
+//- @my_arg4 defines/binding MyArg4
+//- MyArg4.node/kind variable
+//- MyArg4.complete definition
+//- MyArg4 childof MyTask
+task my_task(int my_arg3, int my_arg4);
+ $display(1);
+endtask : my_task
+
+module my_module;
+ initial begin
+ //- @my_function ref MyFunction
+ //- @my_function ref/call MyFunction
+ my_function(2);
+ //- @my_task ref MyTask
+ //- @my_task ref/call MyTask
+ my_task(1);
+ end
+endmodule
diff --git a/verilog/tools/kythe/testdata/more_testdata/macro.sv b/verilog/tools/kythe/testdata/more_testdata/macro.sv
new file mode 100644
index 0000000..d979452
--- /dev/null
+++ b/verilog/tools/kythe/testdata/more_testdata/macro.sv
@@ -0,0 +1,118 @@
+//- _FileNode.node/kind file
+
+//- @PRINT_STRING defines/binding PRINT_STRING
+//- PRINT_STRING.node/kind macro
+//- @#0str1 defines/binding Sr1_PRINT_STRING
+//- Sr1_PRINT_STRING.node/kind variable
+//- Sr1_PRINT_STRING.complete definition
+//- Sr1_PRINT_STRING childof PRINT_STRING
+`define PRINT_STRING(str1) $display("%s\n", str1)
+
+//- @PRINT_3_STRINGS defines/binding PRINT_3_STRINGS
+//- PRINT_3_STRINGS.node/kind macro
+//- @str1 defines/binding Sr1_PRINT_3_STRINGS
+//- Sr1_PRINT_3_STRINGS.node/kind variable
+//- Sr1_PRINT_3_STRINGS.complete definition
+//- Sr1_PRINT_3_STRINGS childof PRINT_3_STRINGS
+//- @str2 defines/binding Sr2_PRINT_3_STRINGS
+//- Sr2_PRINT_3_STRINGS.node/kind variable
+//- Sr2_PRINT_3_STRINGS.complete definition
+//- Sr2_PRINT_3_STRINGS childof PRINT_3_STRINGS
+//- @str3 defines/binding Sr3_PRINT_3_STRINGS
+//- Sr3_PRINT_3_STRINGS.node/kind variable
+//- Sr3_PRINT_3_STRINGS.complete definition
+//- Sr3_PRINT_3_STRINGS childof PRINT_3_STRINGS
+`define PRINT_3_STRINGS(str1, str2, str3) \
+ `PRINT_STRING(str1); \
+ `PRINT_STRING(str2); \
+ `PRINT_STRING(str3);
+
+//- @PRINT_INT defines/binding PRINT_INT
+//- PRINT_INT.node/kind macro
+//- @#0int1 defines/binding Int1_PRINT_INT
+//- Int1_PRINT_INT.node/kind variable
+//- Int1_PRINT_INT.complete definition
+//- Int1_PRINT_INT childof PRINT_INT
+`define PRINT_INT(int1) $display("%d\n", int1)
+
+//- @PRINT_3_INTS defines/binding PRINT_3_INTS
+//- PRINT_3_INTS.node/kind macro
+//- @int1 defines/binding Int1_PRINT_3_INTS
+//- Int1_PRINT_3_INTS.node/kind variable
+//- Int1_PRINT_3_INTS.complete definition
+//- Int1_PRINT_3_INTS childof PRINT_3_INTS
+//- @int2 defines/binding Int2_PRINT_3_INTS
+//- Int2_PRINT_3_INTS.node/kind variable
+//- Int2_PRINT_3_INTS.complete definition
+//- Int2_PRINT_3_INTS childof PRINT_3_INTS
+//- @int3 defines/binding Int3_PRINT_3_INTS
+//- Int3_PRINT_3_INTS.node/kind variable
+//- Int3_PRINT_3_INTS.complete definition
+//- Int3_PRINT_3_INTS childof PRINT_3_INTS
+`define PRINT_3_INTS(int1, int2, int3) \
+ `PRINT_INT(int1); \
+ `PRINT_INT(int2); \
+ `PRINT_INT(int3);
+
+//- @TEN defines/binding TEN
+//- TEN.node/kind macro
+`define TEN 10
+
+//- @NUM defines/binding NUM
+//- NUM.node/kind macro
+//- @#0int1 defines/binding Int1
+//- Int1.node/kind variable
+//- Int1.complete definition
+//- Int1 childof NUM
+`define NUM(int1) int1
+
+package my_pkg;
+ function automatic my_function(int arg1, int arg2);
+ //- @MacroFunction defines/binding MacroFunction
+ //- MacroFunction.node/kind macro
+ `define MacroFunction 10
+ return arg1 + arg2;
+ endfunction
+
+ //- @MacroPackage defines/binding MacroPackage
+ //- MacroPackage.node/kind macro
+ `define MacroPackage 10
+
+ task my_task();
+ //- @MacroTask defines/binding MacroTask
+ //- MacroTask.node/kind macro
+ `define MacroTask 10
+ endtask
+
+ class my_class;
+ //- @MacroClass defines/binding MacroClass
+ //- MacroClass.node/kind macro
+ `define MacroClass 10
+ endclass
+endpackage
+
+module macro;
+ //- @MacroModule defines/binding MacroModule
+ //- MacroModule.node/kind macro
+ `define MacroModule 10
+
+ //- @"`TEN" ref/expands TEN
+ parameter int x = `TEN;
+ initial begin
+
+ //- @"`PRINT_3_STRINGS" ref/expands PRINT_3_STRINGS
+ `PRINT_3_STRINGS("Grand", "Tour", "S4");
+ //- @"`PRINT_3_INTS" ref/expands PRINT_3_INTS
+ `PRINT_3_INTS(1, 2, 3);
+ //- @"`TEN" ref/expands TEN
+ $display("%d\n", `TEN);
+ //- @"`MacroClass" ref/expands MacroClass
+ $display("%d\n", `MacroClass);
+ //- @"`NUM" ref/expands NUM
+ $display("%d\n", `NUM(1));
+ //- @"`TEN" ref/expands TEN
+ //- @"`NUM" ref/expands NUM
+ $display("%d\n", `NUM(`TEN));
+
+ end
+endmodule
diff --git a/verilog/tools/kythe/testdata/more_testdata/module.sv b/verilog/tools/kythe/testdata/more_testdata/module.sv
new file mode 100644
index 0000000..4e89075
--- /dev/null
+++ b/verilog/tools/kythe/testdata/more_testdata/module.sv
@@ -0,0 +1,127 @@
+//- _FileNode.node/kind file
+
+//- @Different_Port_Type defines/binding DifferentPort
+//- DifferentPort.node/kind record
+//- DifferentPort.subkind module
+//- DifferentPort.complete definition
+module Different_Port_Type (
+ ///- @input1 defines/binding InDef
+ //- InDef.node/kind variable
+ //- InDef.complete definition
+ //- InDef childof DifferentPort
+ input input1,
+ //- @wire1 defines/binding WDef
+ //- WDef.node/kind variable
+ //- WDef.complete definition
+ //- WDef childof DifferentPort
+ wire wire1,
+ //- @bit1 defines/binding BDef
+ //- BDef.node/kind variable
+ //- BDef.complete definition
+ //- BDef childof DifferentPort
+ bit bit1
+);
+
+ //- @Different_Port_Type ref DifferentPort
+endmodule : Different_Port_Type
+
+//- @Non_ANSI defines/binding NON_ANSI
+//- NON_ANSI.node/kind record
+//- NON_ANSI.subkind module
+//- NON_ANSI.complete definition
+module Non_ANSI (
+ //- @in1 ref In1Def
+ in1,
+ //- @in2 ref In2Def
+ in2,
+ // - @out1 ref Out1Def
+ out1
+);
+
+ //- @in1 defines/binding In1Def
+ //- In1Def.node/kind variable
+ //- In1Def.complete definition
+ //- In1Def childof NON_ANSI
+ //- @in2 defines/binding In2Def
+ //- In2Def.node/kind variable
+ //- In2Def.complete definition
+ //- In2Def childof NON_ANSI
+ input in1, in2;
+
+ //- @out1 defines/binding Out1Def
+ //- Out1Def.node/kind variable
+ //- Out1Def.complete definition
+ //- Out1Def childof NON_ANSI
+ output out1;
+
+ //- @Non_ANSI ref NON_ANSI
+endmodule : Non_ANSI
+
+
+// TODO(minatoma): add data type forwarding after merging PR #447
+
+//- @my_module defines/binding MyModule
+//- MyModule.node/kind record
+//- MyModule.subkind module
+//- MyModule.complete definition
+module my_module (
+ //- @x defines/binding XDef
+ //- XDef.node/kind variable
+ //- XDef.complete definition
+ //- XDef childof MyModule
+ input x,
+ //- @y defines/binding YDef
+ //- YDef.node/kind variable
+ //- YDef.complete definition
+ //- YDef childof MyModule
+ input wire y,
+ //- @z defines/binding ZDef
+ //- ZDef.node/kind variable
+ //- ZDef.complete definition
+ //- ZDef childof MyModule
+ output z
+);
+
+ //- @w1 defines/binding W1Def
+ //- W1Def.node/kind variable
+ //- W1Def.complete definition
+ //- W1Def childof MyModule
+ //- @w2 defines/binding W2Def
+ //- W2Def.node/kind variable
+ //- W2Def.complete definition
+ //- W2Def childof MyModule
+ //- @w3 defines/binding W3Def
+ //- W3Def.node/kind variable
+ //- W3Def.complete definition
+ //- W3Def childof MyModule
+ wire w1, w2, w3;
+
+ //- @Non_ANSI ref NON_ANSI
+ //- @instance1 defines/binding Instance1Def
+ //- Instance1Def.node/kind variable
+ //- Instance1Def.complete definition
+ //- Instance1Def childof MyModule
+ //- @instance2 defines/binding Instance2Def
+ //- Instance2Def.node/kind variable
+ //- Instance2Def.complete definition
+ //- Instance2Def childof MyModule
+ //- @x ref XDef
+ //- @y ref YDef
+ //- @z ref ZDef
+ //- @w1 ref W1Def
+ //- @w2 ref W2Def
+ //- @w3 ref W3Def
+ Non_ANSI
+ instance1 (
+ x,
+ y,
+ z
+ ),
+ instance2 (
+ w1,
+ w2,
+ w3
+ );
+
+ //- @my_module ref MyModule
+endmodule : my_module
diff --git a/verilog/tools/kythe/testdata/more_testdata/module_with_same_prefix.sv b/verilog/tools/kythe/testdata/more_testdata/module_with_same_prefix.sv
new file mode 100644
index 0000000..9e42c4c
--- /dev/null
+++ b/verilog/tools/kythe/testdata/more_testdata/module_with_same_prefix.sv
@@ -0,0 +1,22 @@
+//- _FileNode.node/kind file
+
+//- @top defines/binding TopModule
+//- TopModule.node/kind record
+//- TopModule.subkind module
+//- TopModule.complete definition
+module top;
+endmodule
+
+//- @top_top defines/binding TopTopModule
+//- TopTopModule.node/kind record
+//- TopTopModule.subkind module
+//- TopTopModule.complete definition
+module top_top;
+
+ //- @#0top ref TopModule
+ //- @top_instance defines/binding TopInstanceDef
+ //- TopInstanceDef.node/kind variable
+ //- TopInstanceDef.complete definition
+ //- TopInstanceDef childof TopTopModule
+ top top_instance ();
+endmodule
diff --git a/verilog/tools/kythe/testdata/more_testdata/package.sv b/verilog/tools/kythe/testdata/more_testdata/package.sv
new file mode 100644
index 0000000..d69ee53
--- /dev/null
+++ b/verilog/tools/kythe/testdata/more_testdata/package.sv
@@ -0,0 +1,120 @@
+//- _FileNode.node/kind file
+
+//- @my_pkg1 defines/binding MyPkg1
+//- MyPkg1.node/kind package
+package my_pkg1;
+ //- @w1 defines/binding W1Def
+ //- W1Def.node/kind variable
+ //- W1Def.complete definition
+ //- W1Def childof MyPkg1
+ wire w1;
+
+ //- @my_class1 defines/binding MyClass1
+ //- MyClass1.node/kind record
+ //- MyClass1.complete definition
+ //- MyClass1 childof MyPkg1
+ class my_class1;
+
+ //- @my_function1 defines/binding MyFunction1
+ //- MyFunction1.node/kind function
+ //- MyFunction1.complete definition
+ //- MyFunction1 childof MyClass1
+ function int my_function1();
+ return 1;
+ endfunction
+ endclass
+
+ //- @my_function2 defines/binding MyFunction2
+ //- MyFunction2.node/kind function
+ //- MyFunction2.complete definition
+ //- MyFunction2 childof MyPkg1
+ function int my_function2();
+ return 1;
+ endfunction
+
+ //- @my_pkg1 ref MyPkg1
+endpackage : my_pkg1
+
+//- @my_pkg2 defines/binding MyPkg2
+//- MyPkg2.node/kind package
+package my_pkg2;
+
+ //- @w2 defines/binding W2Def
+ //- W2Def.node/kind variable
+ //- W2Def.complete definition
+ //- W2Def childof MyPkg2
+ wire w2;
+
+ //- @my_class_in_pkg2 defines/binding MyClassPkg2
+ //- MyClassPkg2.node/kind record
+ //- MyClassPkg2.complete definition
+ //- MyClassPkg2 childof MyPkg2
+ class my_class_in_pkg2;
+ endclass
+
+endpackage
+
+//- @my_module defines/binding MyModule
+//- MyModule.node/kind record
+//- MyModule.subkind module
+//- MyModule.complete definition
+module my_module (
+ input x
+);
+ //- @#0my_pkg1 ref/imports MyPkg1
+ //- @#1my_pkg1 ref/imports MyPkg1
+ //- @my_class1 ref MyClass1
+ //- @my_function2 ref MyFunction2
+ import my_pkg1::my_class1, my_pkg1::my_function2;
+
+ //- @my_pkg2 ref/imports MyPkg2
+ //- @my_class_in_pkg2 ref MyClassPkg2
+ import my_pkg2::my_class_in_pkg2;
+
+ //- @my_function2 ref MyFunction2
+ //- @my_function2 ref/call MyFunction2
+ initial $display(my_function2());
+endmodule
+
+//- @second_module defines/binding MyModule1
+//- MyModule1.node/kind record
+//- MyModule1.subkind module
+//- MyModule1.complete definition
+module second_module;
+ //- @my_pkg1 ref/imports MyPkg1
+ import my_pkg1::*;
+ //- @my_pkg3 ref/imports MyPkg3
+ import my_pkg3::*;
+
+ //- @my_module ref MyModule
+ //- @instance1 defines/binding MyModuleInstance
+ //- MyModuleInstance.node/kind variable
+ //- MyModuleInstance.complete definition
+ //- MyModuleInstance childof MyModule1
+ //- @w1 ref W1Def
+ my_module instance1 (w1);
+
+ //- @my_function3 ref MyFunction3
+ //- @my_function3 ref/call MyFunction3
+ initial $display(my_function3());
+endmodule
+
+//- @my_pkg3 defines/binding MyPkg3
+//- MyPkg3.node/kind package
+package my_pkg3;
+
+ //- @my_class_pkg3 defines/binding MyClassPkg3
+ //- MyClassPkg3.node/kind record
+ //- MyClassPkg3.complete definition
+ //- MyClassPkg3 childof MyPkg3
+ class my_class_pkg3;
+ endclass
+
+ //- @my_function3 defines/binding MyFunction3
+ //- MyFunction3.node/kind function
+ //- MyFunction3.complete definition
+ //- MyFunction3 childof MyPkg3
+ function int my_function3();
+ return 6;
+ endfunction
+endpackage
