)]}'
{
  "id": "f361e94baa0461948a70f916bb01040889531659",
  "repo": "third_party/verible",
  "revision": "e2f5318e4eca85f65dbfcfb9228f3d63e0392286",
  "path": "verilog/CST/expression_test.cc"
}
