)]}'
{
  "id": "74bcf8c155c574e7295a21c3c1e820fd35e4faf9",
  "repo": "third_party/verible",
  "revision": "e2f5318e4eca85f65dbfcfb9228f3d63e0392286",
  "path": "verilog/analysis/checkers/disable_statement_rule.cc"
}
